FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms

Call for Papers

Field-programmable gate arrays (FPGAs) provide an alternative route to high-performance computing where fine-grained synchronisation and parallelism are achieved with lower power consumption and higher performance than just microprocessor clusters. With microprocessors facing the ‘processor power wall problem’ and application specific integrated circuits (ASICs) requiring expensive VLSI masks for each algorithm realisation, FPGAs bridge the gap by offering flexibility as well as performance. FPGAs at 65nm and below have enough resources to accelerate many computationally complex algorithms used in simulations. Moreover, recent times have witnessed an increased interest in design of FPGA-based supercomputers.

This special issue is intended to present current state-of-the-art and most recent developments in FPGA-based supercomputing platforms and in using FPGAs to accelerate computationally complex simulations. Topics of interest include, but are not limited to, FPGA-based supercomputing platforms, design of high-throughput area time-efficient FPGA implementations of algorithms, programming languages, and tool support for FPGA supercomputing. Together these topics will highlight cutting-edge research in these areas and provide an excellent insight into emerging challenges in this research perspective. Papers are solicited in any of (but not limited to) the following areas:

  • Architectures of FPGA-based supercomputers
    • History and surveys of FPGA-based supercomputer architectures
    • Novel architectures of supercomputers, including coprocessors, attached processors, and hybrid architectures
    • Roadmap of FPGA-based supercomputing
    • Example of acceleration of large applications/ simulations using FPGA-based supercomputers
  • FPGA implementations of computationally complex algorithms
    • Developing high-throughput FPGA implementations of algorithms
    • Developing area time-efficient FPGA implementations of algorithms
    • Precision analysis for algorithms to be implemented on FPGAs
  • Compilers, languages, and systems
    • High-level languages for FPGA application development
    • Design of cluster middleware for FPGA-based supercomputing platforms
    • Operating systems for FPGA-based supercomputing platforms

Prospective authors should follow the EURASIP Journal on Embedded Systems manuscript format described at the journal site http://www.hindawi.com/journals/es/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/, according to the following timetable:

Manuscript DueJuly 1, 2008
First Round of ReviewsOctober 1, 2008
Publication DateJanuary 1, 2009

Guest Editors:

  • Vinay Sriram, Defence and Systems Institute, University of South Australia, Adelaide, SA 5001, Australia
  • David Kearney, School of Computer and Information Science, University of South Australia, Adelaide, SA 5001, Australia
  • Lakhmi Jain, School of Electrical and Information Engineering, University of South Australia, Adelaide, SA 5001, Australia
  • Miriam Leeser, School of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA