Formal Techniques for Embedded Systems Design and Validation
Call for Papers
Computing platforms that are embedded within larger systems they control, called embedded systems, are inherently very complex as they are responsible for controlling and regulating multiple system functionalities. Often embedded systems are also safety-critical requiring high degree of reliability and fault tolerance. Examples include distributed microprocessors controlling the modern cars or aircrafts and airport baggage handling system that track and trace unsafe baggage. To address this growing need for safety and reliability, formal techniques are increasingly being adapted to suit embedded platforms. There has been widespread use of synchronous languages such as Esterel for the design of automotive and flight control software that requires stronger guarantees. Languages like Esterel not only provide nice features for high-level specification but also enable model checking-based verification due to their formal semantics. Other semiformal notations are also being proposed as standards to specify industrial embedded systems using, for example, the newly developed IEC61499 standard for process control. This standard primarily focuses on component-oriented description of embedded control systems. The goal of this special issue is to bring together a set of high-quality research articles looking at different applications of formal or semiformal techniques in specification, verification, and synthesis of embedded systems.
Topics of interest are (but not limited to):
- Verification of system-level languages
- Verification of embedded processors
- Models of computation and verification
- Models of computation for heterogeneous embedded systems
- IP verification issues
- Open system verification techniques such as module checking and applications of module checking
- Formal techniques for protocol matching and interface process generation
- Applications of DES control theory in open system verification
- Adaptive techniques for open system verification
- Verification techniques for automatic debugging of embedded systems
- Formal approaches for secure embedded systems
- Hardware-software coverification of embedded systems
- Compositional approaches for SOC verification
- Verification of distributed embedded system
Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/es/guidelines.html. Authors should follow the EURASIP Journal on Embedded Systems manuscript format described at the journal's site http://www.hindawi.com/journals/es/. Prospective authors should submit an electronic copy of their complete manuscript through the journal's Manuscript Tracking System at http://mts.hindawi.com/, according to the following timetable:
| Manuscript Due | August 1, 2008 |
| First Round of Reviews | November 1, 2008 |
| Publication Date | February 1, 2009 |
Guest Editors:
- Partha S. Roop, Department of Electrical & Computer Engineering, University of Auckland, Auckland 1142, New Zealand
- Samik Basu, Department of Computer Science, Iowa State University, Ames, IA 50011, USA
- Chong-Min Kyung, Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, South Korea
- Gregor Goessler, INRIA Grenoble-Rhône-Alpes, 38334 Saint Ismier Cedex, France