The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

Quadir, N. A.; Jain, Amit; Kashfi, S.; Albasha, Lutfi; Qaddoumi, Nasser

doi:https://doi.org/10.1049/2023/2265697

IET Circuits, Devices & Systems

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Research Article | Open Access

Volume 2023 | Article ID 2265697 | https://doi.org/10.1049/2023/2265697

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

N. A. Quadir,¹Amit Jain,²S. Kashfi,¹Lutfi Albasha,¹and Nasser Qaddoumi¹

Academic Editor: Euclides Lourenco Chuma

Received24 Jul 2023

Revised25 Aug 2023

Accepted03 Oct 2023

Published31 Oct 2023

Abstract

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

1. Introduction

Bandwidth and modulation play significant roles in designing power amplifiers for high-speed communications. This helps in delivering faster and superior RF (radio frequency) performances. Several power amplifier designs are reported without a linearizer, examples include cascode [1–5], three stage common source [6], two stage current mirror [7], and triple stacked single stage transistors [8]. These designs allow for bigger bandwidth, higher gain, and better power handling capabilities. However, linearity is one of the key parameters in the design of power amplifier to overcome distortion of the transmitted signal. Several design techniques are reported in the literature to improve power amplifiers linearity [9–12]. Applications where operating frequency is less than 10 GHz, linearization techniques such as feed forward and cartesian feedback are mostly used [13]. However, these systems are complex and less suitable for handset integration. Predistortion techniques may offer a better and lower cost alternative with the linearizer employed in predistortion techniques models the inverse characteristic of the nonlinearities in the power amplifier to compensate for linearity and gain. In higher frequency bands, the circuits using digital predistortion technique consumes more power due to higher clock rates. Hence analog predistortion [14–16], which can be divided as active and passive, are seen as a better alternative. Passive analog predistortion is less complex compared to its active counterpart and does not obviously add any gain, however it does improve the linearity, and is considered as a better option for high-frequency applications [17–21].

A dual stage power amplifier integrated with analog linearizer circuit on a single substrate is presented in this paper. The performance of the designed circuit is presented across process, voltage and temperature variations with Monte Carlo simulations results to assess the long-term reliability of the proposed amplifier.

2. Proposed Design

Figure 1 depicts the schematic of the design that consists of biasing network, input and output impedance matching circuit and the integrated linearizer circuit with the power amplifier. For the design of impedance matching of inter and input stage, small signal S-parameter analysis is used. Stability of the designed power amplifier is improved by using a resistor in the interstage impedance matching network. The resistor slightly reduces the gain and hence boosts the amplifier stability. Furthermore, all the component values are optimized in the matching network to achieve the desired result. Transistors Q3, Q4, and Q5, Q6 form the 1st and 2nd stage of the biasing circuit, respectively. The biasing circuits are basically simple voltage divider circuits. This helped to ensure lower power consumption and hence improving the efficiency of the amplifier. Proper care is taken in choosing the values of these biasing transistors, to avoid loading the previous stages with more parasitic capacitance. Table 1 provides the values of all the components used in the design.

In the design of a power amplifier following steps are taken:(1)At first the output stage is designed, where maximum voltage swing allowed for the given technology is determined from the load line graphs, such that the drain voltage swings equally between V_max and V_DS,sat centered at power supply. Maximum voltage swing is governed by the breakdown for the given technology used and is given by(2)Based on the output voltage swing and P_1 dB requirements, biasing current of the transistor is set and from that aspect ratio of the transistors are obtained. Load-line theory is used to determine P_1 dB and is given byFor power gain based on the small signal model of the transistor as shown in Figure 2 is given by Equation (2) [22].Transistor aspect ratio is designed as such as to maximize the power gain as given by Equation (3). The resistance at the gate must be reduced by implementing less number of finger in the length of the designed gate which is done in the proposed design. The gain of the power amplifier also tends to decrease with the increase in temperature. In order to have minimum effect of temperature on gain the transconductance of the amplifier is designed using the given equations.where W is the width of the transistor, µ_n is the mobility of electrons in the NMOS transistor, gate oxide capacitance is given by C_ox, length of the transistor is given by L, gate-source voltage is given by V_gs, and threshold voltage is denoted by V_t, T₀ is 300 K, and T is the operating temperature.(3)After that output matching network is designed for the last stage and for the preceding stages to maximize power transfer.(4)Same steps are repeated for the design of the preceding stages.(5)Input stage is then matched to Z_o = 50.(6)Cold-mode MOSFET technique to increase the linearity is then implemented.

A linearizer technique of cold-mode MOSFET [14–20] is implemented in the design. It not only improves the linearity of the design but also improves the gain at higher frequency bands. The linearizer circuit consists of MOSFET Q7, three resistors R1, R2, and R3 and two capacitors C6 and C7 as noticed from Figure 1. The resistors are being used as the bias feed for the respective bias circuits and capacitors are used as bypass capacitors. The designed linearizer circuit successfully implements the desired predistortion characteristics by using the difference in I–V characteristics slope between linear and saturation region. To achieve better linearity, gate voltage at the driver transistor must be equal to the source potential of the transistor used for linearization [21, 23, 24] Cold-mode linearizer’s equivalent circuit [25–27] is shown in Figure 3, in which the circuit is represented as the combination of two parallel branches, where one consists of a variable resistor R_ds and the other is a series connection of resistor R_eq and capacitor C_eq. R_ds represents the active device Q7 whose resistance is proportional to the power level of the input, which in turn results in the gain expansion characteristics. Considering the variations of C_eq and R_eq to be much smaller than the variation of R_ds the gain S₂₁ is expressed by Equation (6):where 50 Ω characteristics impedance is denoted by Z₀ and R_ds (drain to source resistor). Equation (7) shows that at low-input power, R_ds is almost constant due to linear region operation of the transistor and increase in R_ds happens near the saturation region (pinch-off voltage), when the input power is high. It can be perceived that increased R_ds results in gain expansion which is the most important parameter of linearizer and is expressed as follows:

3. Results

The proposed circuit has been designed in 65-nm CMOS technology with both simulated (without parasitic components) and extracted (with all the parasitic RC components) views compared for various important parameters of PA. S21 (gain) and S11 (input reflection coefficient) are depicted in Figure 4; S21 peak is achieved at 28 GHz after which it starts to gradually reduce. It can be observed from the figure that the simulation and extracted result for input reflection coefficient remains almost the same for the entire frequency range.

The overall power gain (Equation (8)) of the designed circuit is illustrated in Figure 5, for the input power ranging from −20 to 15 dBm.where overall power gain is expressed by A and P_in and P_out are the input and output power levels, respectively.

The result shows the power gain of 21 dB whereas the extracted result is obtained as 14 dB. The difference in the achieved powers shows the effect of the additional parasitics the layout has generated based on the process PDK, and its impact on the output matching.

The power-added efficiency (PAE) (Equation (9)) for the designed circuit with linearizer is obtained as 17% as plotted in Figure 4.

The linearity of the designed circuit is assessed by plotting the 1-dB compression point versus the input power levels. As observed in Figure 6 the 1-dB compression point achieved was 19.2 and 18.6 dBm for simulated and extracted circuits, respectively.

The ACPR given by Equation (10) is an important metric used to quantify the nonlinear behavior displayed by the power amplifier that normally comes into picture when PAs are operated beyond their linear region at slightly compressed mode, to increase its efficiency.

ACPR with and without built-in linearizer is shown in Figures 7 and 8, respectively, showing clear improvement in linearity.

To obtain ACPR for various standards, the offset frequency and the channel bandwidth (main) is kept at 20 MHz [28]. It can be observed that the ACPR value reduces as the input power level reaches 1-dB compression point. Figure 9 demonstrates the ACPR values of the power amplifier with and without linearizer. It is evident from the plot that the ACPR values significantly improves till 1-dB compression point.

Emphasis on reliability and PVT (process, voltage, and temperature) variations were discussed in the recent works [29–33]. To evaluate the designed circuit for these corners, Monte Carlo simulations were performed across five corner simulations (SS, SF, TT, FS, and FF). Figure 10 illustrates the effect of process variations on PAE of the amplifier. As noticed from Figure 10(a) the maximum PAE is achieved in fast–slow (FS) corner and minimum PAE is obtained in slow–slow (SS) corner. The design circuit is also simulated for power gain under the process variation (Figure 10(b)). The simulation shows the maximum power gain is achieved as 21.5 dB considering fast–fast (FF) combination, whereas the minimum value of 16.9 dB is obtained for slow–fast (SF) case.

(a)

(b)

A change of 5 dB is seen across the temperature variation of −40 and 125°C similarly a difference of 5% is seen in PAE across the temperature variation as shown in Figure 11. The maximum PAE of 18.5% is obtained at −40°C, after which the performance degrades with temperature showing the minimum value as 13% at 125°C.

The variation of the power gain with respect to power supply variation is shown in Figure 12. The maximum and minimum values of power gain obtained were 20.3 and 18.5 dB, respectively. The PAE curve shows a parabolic behavior with the maximum value of 17.8%, whereas the minimum value was 15.3%. This is a reasonable amount of PAE given the process capabilities. PVT corner analysis has, hence, confirmed a very good performance of the designed power amplifier in compliance with related standards under variations of temperature, voltage supply and process.

Finally, the designed circuit has been assessed by Monte Carlo simulation (100 runs) to check its performance for various changes across the process. The standard deviation of PAE was measured to be 4.2% with mean value of 15.8% as appears in histogram in Figure 13(a). The reported mean of power gain is 20.5 dB and the standard deviation is 4.5 dB as illustrated in Figure 13(b). This is a particularly good result and is also done for the first time in this work for a linearized power amplifier.

(a)

(b)

To reduce the chip size and noise in the circuit, lumped elements were not integrated onto the chip [34]. However, while designing these lumped elements the offchip impedances such as board capacitance, wire-bond inductance, and PCB (printed circuit board) line capacitances were taken care of. By keeping these elements offchip, it also enables the tuning ability of the matching network with an added advantage of small chip size and being economical. Layout of the chip is shown in Figure 14 and the size of the entire chip without the offchip components is 525 ×450 µm².

Table 2 presents a comparison between published work and this design. Most of the work it has been compared to are power amplifiers without any built-in linearizers as most of the design with linearization techniques are operating around 2–5 GHz, however the study of Kuo et al. [9] and Tsai et al. [14] are power amplifiers with linearization techniques operating at comparable speed or higher. Adaptive bias technique is used by Kuo et al. [9] to increase the efficiency and linearity, but the design consumes around 108 mW of power which is around 60% more than our design. The design by Tsai et al. [14] uses cold-mode MOSFET linearizer with body biasing technique operating at 60 GHz but the total power consumption of the design is around 102 mW which in comparison to our design is more than 60%. Values of most of the critical parameter achieved by our design is around 50% or more in comparison to the work (built-in linearizers) which have measured results. With reference to Table 2, this work reports the highest 1-dB compression point, with the value of gain, p_sat (saturated power level) and PAE are also similar to the numbers which is obtained through other linearizers through the use of cold-mode MOSFET linearizer.

4. Conclusions

In this paper a new analog cold-mode linearized power amplifier was designed and evaluated using 65-nm RFCMOS process. An excellent PAE of 17.1% was obtained by the proposed design. A built-in linearizer was used to obtain the OIP_1 dB (output referred P₁ _dB) of 18.6 dBm. The linearity in terms of compression point (P_1 dB) is better in comparison to the other available work at such frequency. The design has shown at least 10 dB improvement in adjacent channel rejection ratio ACPR of the power amplifier with the linearizer implemented. Maximum small-signal gain of 21.1 dB has been achieved with this design. The result shows that the maximum value of the output power provided by the design is 22 dBm under process and temperature variations. This proves that the design is highly robust against physical and environmental variations. Monte Carlo simulations result, another novel contribution in this work, shows good performance against statistical variations. It confirms that using this analog predistorted technique can be an attractive solution for millimeter wave high-power applications which has been already proved by Tsai et al. [14], however this paper further delve into the process reliability analysis of the power amplifier by providing the PVT variations and Monte Carlo reliability simulation results on the key parameters of the design.

Data Availability

All the design and results data are available, however due to university’s policy we will not able to share it.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

References

H. R. Khan and Q. Wahab, “A 24 GHz Class-A power amplifier in 0.13 um CMOS technology,” in 2011 3rd International Conference on Computer Research and Development, pp. 314–317, IEEE, Shanghai, China, 2011.
View at: Publisher Site | Google Scholar
H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, “Millimeter-wave CMOS circuit design,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 2, pp. 472–477, 2005.
View at: Publisher Site | Google Scholar
A. Komijani, A. Natarajan, and A. Hajimiri, “A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1901–1908, 2005.
View at: Publisher Site | Google Scholar
H. Portela, V. Subramanian, and G. Boeck, “Fully integrated high efficiency K-band PA in 0.18 µm CMOS technology,” in 2009 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC), pp. 393–396, IEEE, Belem, Brazil, 2009.
View at: Publisher Site | Google Scholar
Y.-N. Jen, J.-H. Tsai, C.-T. Peng, and T.-W. Huang, “A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 µm CMOS process,” IEEE Microwave and Wireless Components Letters, vol. 9, no. 1, pp. 42–44, 2009.
View at: Publisher Site | Google Scholar
J. W. Lee and S. M. Heo, “A 27 GHz, 14 dBm CMOS power amplifier using 0.18 µm common-source MOSFETs,” IEEE Microwave and Wireless Components Letters, vol. 18, no. 11, pp. 755–757, 2008.
View at: Publisher Site | Google Scholar
C.-Y. Wu, S.-W. Hsu, and W.-C. Wang, “A 24-GHz CMOS current-mode power amplifier with high PAE and output power,” in 2007 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2866–2869, IEEE, New Orleans, LA, USA, 2007.
View at: Publisher Site | Google Scholar
J. Chang, K. Kim, S. Lee, and S. Nam, “24 GHz stacked power amplifier with optimum inter-stage matching using 0.13 µm CMOS process,” in 2011 3rd International Asia-Pacific Conference on Synthetic Aperture Radar (APSAR), pp. 1–3, IEEE, Seoul, Korea (South), 2011.
View at: Google Scholar
N.-C. Kuo, J.-C. Kao, C.-C. Kuo, and H. Wang, “K-band CMOS power amplifier with adaptive bias for enhancement in back-off efficiency,” in 2011 IEEE MTT-S International Microwave Symposium, pp. 1–4, IEEE, Baltimore, MD, USA, 2011.
View at: Publisher Site | Google Scholar
J. Yi, Y. Yang, M. Park, W. Kang, and B. Kim, “Analog predistortion linearizer for high-power RF amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 48, no. 12, pp. 2709–2713, 2000.
View at: Publisher Site | Google Scholar
C.-C. Huang and W.-C. Lin, “A compact high-efficiency CMOS power amplifier with built-in linearizer,” IEEE Microwave and Wireless Components Letters, vol. 19, no. 9, pp. 587–589, 2009.
View at: Publisher Site | Google Scholar
L. Albasha, C. Clifton, Y. Jingu et al., “An ultra-wideband digitally programmable power amplifier with efficiency enhanacement for cellular and emerging wireless communication standards,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 10, pp. 1579–1591, 2016.
View at: Publisher Site | Google Scholar
S. Ock, H. Song, and R. Gharpurey, “A Cartesian feedback-feedforward transmitter in 130 nm CMOS,” in 2015 IEEE Custom Integrated Circuits Conference (CICC), pp. 1–4, IEEE, San Jose, CA, USA, 2015.
View at: Publisher Site | Google Scholar
J.-H. Tsai, C.-H. Wu, H.-Y. Yang, and T.-W. Huang, “A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer,” IEEE Microwave and Wireless Components Letters, vol. 21, no. 12, pp. 676–678, 2011.
View at: Publisher Site | Google Scholar
N. A. Quadir, S. Kashfi, A. Jain, and L. Albasha, “Millimeter-wave analog pre-distorted power amplifier at 65 nm node,” in 2019 International Conference on Communications, Signal Processing, and their Applications (ICCSPA), pp. 1–4, IEEE, Sharjah, United Arab Emirates, 2019.
View at: Publisher Site | Google Scholar
S. Alluri, N. Rostomyan, V. Leung, and P. Asbeck, “A Ka band power amplifier with varactor-based analog predistortion in pMOS-SOI,” in 2022 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR), pp. 42–45, IEEE, Las Vegas, NV, USA, 2022.
View at: Publisher Site | Google Scholar
T.-Y. Huang, Y.-H. Lin, and H. Wang, “A K-Band adaptive-bias power amplifier with enhanced linearizer using 0.18-µm CMOS process,” in 2015 IEEE MTT-S International Microwave Symposium, pp. 1–3, IEEE, Phoenix, AZ, USA, 2015.
View at: Publisher Site | Google Scholar
J.-H. Tsai, H.-Y. Yang, C.-C. Kuo, and T.-W. Huang, “A miniature 38-48 GHz MMIC sub-harmonic transmitter with post-distortion linearization,” in 2007 IEEE/MTT-S International Microwave Symposium, pp. 1133–1136, IEEE, Honolulu, HI, USA, 2007.
View at: Publisher Site | Google Scholar
J.-H. Tsai, H.-Y. Chang, P.-S. Wu, Y.-L. Lee, T.-W. Huang, and H. Wang, “Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 6, pp. 2487–2496, 2006.
View at: Publisher Site | Google Scholar
T. McConaghy, K. Breen, J. Dyck, and A. Gupta, Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide, Springer Verlag, New York, 2013.
K.-Y. Kao, Y.-C. Hsu, K.-W. Chen, and K.-Y. Lin, “Phase-delay cold-FET pre-distortion linearizer for millimeter-wave CMOS power amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 12, pp. 4505–4519, 2013.
View at: Publisher Site | Google Scholar
D. M. Pozar, Microwave Engineering, Wiley, New York, 1998.
Z. Sun, Z. Liu, T. Wu, H. Yu, Y. Chen, and S. Ma, “A 33-37GHz two-path power amplifier with >18-dB Gain and 26.7-dBm PSAT in 150 nm GaAs process,” in 2022 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 64–67, IEEE, Shenzhen, China, 2022.
View at: Publisher Site | Google Scholar
F. Meng, K. Li, D. J. Thomson, C. Lacava, P. Wilson, and G. T. Reed, “Ultra wide-band inductive peaking VCO with cascode noise reduction,” in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, IEEE, Florence, Italy, 2018.
View at: Publisher Site | Google Scholar
H. Koo, B. Koo, and S. Hong, “Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit,” in 2012 Asia Pacific Microwave Conference Proceedings, pp. 7–9, IEEE, Kaohsiung, Taiwan, 2012.
View at: Publisher Site | Google Scholar
J.-L. Kuo, Z.-M. Tsai, and H. Wang, “A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-μm CMOS technology,” in 2008 38th European Microwave Conference, pp. 1425–1428, Amsterdam, Netherlands, 2008.
View at: Publisher Site | Google Scholar
A. Sarkar and B. Floyd, “A 28-GHz class-J power amplifier with 18-dBm output power and 35% peak PAE in 120-nm SiGe BiCMOS,” in 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in Rf Systems, pp. 71–73, IEEE, Newport Beach, CA, USA, 2014.
View at: Publisher Site | Google Scholar
L. Wang, The design and Linearization of 60 GHz Injection Locked Power Amplifier, Lund University, Lund, Sweden, 2016.
N. A. Quadir, L. Albasha, M. Taghadosi, N. Qaddoumi, and B. Hatahet, “Low-power implanted sensor for orthodontic bond failure diagnosis and detection,” IEEE Sensors Journal, vol. 18, no. 7, pp. 3003–3009, 2018.
View at: Publisher Site | Google Scholar
I. Ghorbel, F. Haddad, W. Rahjandribe, and M. Loulou, “A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations,” Analog Integrated Circuits and Signal Processing, vol. 93, pp. 415–426, 2017.
View at: Publisher Site | Google Scholar
Y. Siddiqi, S. A. Jawed, and N. Ahmed, “PVT-tolerant current reference generation using different PTAT currents,” Microelectronics Journal, vol. 66, pp. 112–118, 2017.
View at: Publisher Site | Google Scholar
K. V. Reddy and K. H. Prasantha, “Inductor-less PVT robust gain switching balun LNA for multi standard applications,” International Journal of Electronics, vol. 106, no. 9, pp. 1412–1426, 2019.
View at: Publisher Site | Google Scholar
R. Sanjay, K. H. Kumar, and B. Venkataramani, “A PVT compensated nano-ampere current reference in 0.18 µm CMOS,” Analog Integrated Circuits and Signal Processing, vol. 98, no. 3, pp. 615–625, 2019.
View at: Publisher Site | Google Scholar
Y. Shang, H. Xu, J. Mo et al., “The design and thermal reliability analysis of a high-efficiency K-Band MMIC medium-power amplifier with multiharmonic matching,” Active and Passive Electronic Components, vol. 2016, Article ID 6295405, 7 pages, 2016.
View at: Publisher Site | Google Scholar
R. Ciocoveanu, R. Weigel, A. Hagelauer, A. Geiselbrechtinger, and V. Issakov, “5G mm-wave stacked class AB power amplifier in 45 nm PD-SOI CMOS,” in 2018 Asia-Pacific Microwave Conference (APMC), pp. 147–149, IEEE, Kyoto, Japan, 2018.
View at: Publisher Site | Google Scholar

Copyright

Copyright © 2023 N. A. Quadir et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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