A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Table 1

Experiments design for field plate profile optimization.

Silicon loss	Group 1; ∼200 A	Group 2; ∼50 A	Group 3; ∼0 A	Group 4; ∼−100 A; (oxide remains)
Bias power	Baseline	−4.2%	Baseline	−4.2%
Etching time	Baseline	Baseline	−12%	−12%
Extra HF	–	–	∼15 A	∼150 A
TEM cut (Figure 6)	√	√	√	√
TEM cut (Figure 7)	√	○	○	√