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International Journal of Digital Multimedia Broadcasting
Volume 2010 (2010), Article ID 730509, 10 pages
Mixed-Signal Parallel Compressive Spectrum Sensing for Cognitive Radios
1Department of Electrical and Computer Engineering, The Analog and Mixed Signal Center (AMSC), Texas A&M University, College Station, TX 77843-3128, USA
2Army Research Laboratory, AMSRD-ARL-CI-CN, Adelphi, MD 20783, USA
Received 2 December 2009; Accepted 30 January 2010
Academic Editor: Fred Daneshgaran
Copyright © 2010 Zhuizhuan Yu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Wideband spectrum sensing for cognitive radios requires very demanding analog-to-digital conversion (ADC) speed and dynamic range. In this paper, a mixed-signal parallel compressive sensing architecture is developed to realize wideband spectrum sensing for cognitive radios at sub-Nqyuist rates by exploiting the sparsity in current frequency usage. Overlapping windowed integrators are used for analog basis expansion, that provides flexible filter nulls for clock leakage spur rejection. A low-speed experimental system, built with off-the-shelf components, is presented. The impact of circuit nonidealities is considered in detail, providing insight for a future integrated circuit implementation.
Cognitive Radio (CR), first proposed in , provides a new paradigm to improve spectrum efficiency by enabling Dynamic Spectrum Access (DSA). In CR, spectrum holes that are unoccupied by primary users can be assigned to appropriate secondary users as long as the interference introduced by secondary users is not harmful to the primary users [2–4]. The design of cognitive radio networks is a complicated cross-layer procedure . In this paper, we focus on the spectrum sensing problem in CR, in which sensing and detection of primary users is done in order to realize Dynamic Spectrum Access.
Spectrum sensing can be a very challenging task for CR due to many factors. First, for the sake of improving the frequency usage efficiency, the sensing bandwidth for CR can expand from hundreds of MHz to several GHz. Second, the sensing radio should be able to detect very weak primary users, which arise due to fading and the hidden terminal problem . With traditional time-domain Nyquist sampling, sensors are needed with both wide bandwidth and high dynamic range, stressing technology, and demanding higher power [6, 7]. Conventional wideband sensing with a high-speed and high-resolution ADC becomes less appealing as the bandwidth becomes significant. Alternative approaches, such as a fixed bank of analog filters followed by parallel ADCs, impose strict requirements on the filter design.
It has been observed that today's spectrum usage presents some sparsity in the sense that only a small portion of the available frequency bands are heavily loaded while others are partially or rarely occupied . This frequency usage sparsity can be exploited under the framework of Compressed Sensing (CS) [8, 9] to effectively reduce the sampling rate. The sparse signal can be captured via projection over a random basis that is incoherent with respect to the signal basis, and perfect signal reconstruction from these projections can be obtained with high probability, where the number of random projections is on the order of the signal's information rate rather than the Nyquist rate.
The idea of applying CS for wideband spectrum sensing was reported, for example, in . However, this approach assumes full-rate analog-to-digital conversion which does not reduce the complexity of the spectrum sensing receiver. We have proposed a mixed-signal parallel segmented compressive sensing (PSCS) architecture for wideband spectrum sensing , where the high-speed ADCs were avoided by carrying out an analog basis expansion in parallel before sampling. In this paper we elaborate on the idea of applying the PSCS front-end , with special emphasis on implementation issues such as spurious frequency tones, timing, and other mismatches. First, we show that the proposed overlapping windowed integration in the PSCS architecture provides a scheme to mitigate the spurs due to clock leakage by setting the lowpass filter nulls flexibly, which is favorable for practical implementation. Second, a low-speed prototype built with off-the-shelf components is presented in detail from the overall system configuration to building blocks, in which practical constraining issues are addressed.
The remainder of the paper is organized as follows. A brief background on CS is provided in Section 2 and the spectral occupancy signal modeling is given in Section 3. Section 4 introduces the mixed-signal parallel compressive spectrum sensing scheme. Section 5 discusses the spurious frequency rejection schemes in the PSCS front-end. A low-speed prototype is introduced in Section 6. Conclusions are made in Section 7.
2. Compressive Sensing Background
A signal that is spanned by basis functions (), that is, , or in the matrix form , is a K-sparse signal if only out of the coefficients are nonzero at any time, where . A signal is compressible if its approximation error by a K-sparse signal decays exponentially as increases.
According to CS theory, a signal that is sparse or compressible over a known basis can be sampled and reconstructed at sub-Nyquist rate, and the sampling rate reduction depends on the signal's sparsity and the reconstruction algorithms. Specifically, the sub-Nyquist rate sampling is achieved by projecting the signal into a transform-domain over which the sampling operation occurs, which is different from the traditional way of sampling the signal in the time-domain. Mathematically, this procedure can be described as , where are the collected samples, and is incoherent with which is the basis for the transform-domain. The reconstruction of the original signal relies on the estimation of the coefficients , which is obtained by solving the following optimization problems, for which many convex optimization techniques or iterative greedy algorithms can be used:(i)noiseless case: (ii)noisy case: where is the error due to the noise.
Note that, in this paper, we generally do not differentiate between sparse and compressible unless specifically noted.
3. Signal Modeling
The received signal is a modeled as a multiband analog signal whose spectrum is illustrated in Figure 1. Specifically, we assume that , with a frequency span from to , is the superposition of primary users, perhaps using different wireless standards . Each wireless standard occupies a certain finite frequency band which consists of multiple channels. According to the measurements done by FCC in the US , in many cases the current frequency usage exhibits sparsity because only a part of the allocated channels is utilized at a given time.
Without loss of generality, we assume that is bandlimited to ; so can be written as
where is the Fourier transform of .
where is the resolution on the frequency axis and . In other words, is approximated as a multicarrier signal bandlimited to and with a carrier spacing of . The sparse frequency occupancy means that statistically, speaking, only out of the carriers are active at any time, where . The multicarrier model is convenient for representing user occupancy with spectral sparsity. Comparing (3) and (4), we notice that this model is based on a finite dimensional approximation of the signal spectrum. Since there are unknowns where in (4) and change every seconds, the model in (4) is a case of a Finite Rate of Innovation (FRI) model in which the innovation locations lie on the Nyquist grid. For clarity, we rewrite (4) as
where is additive white Gaussian noise (AWGN), , , , , and has only nonzero elements. Since is a scalar, for simplicity, we discard it in the rest of the paper. The spectrum hole detection, for example, energy or feature detection, is usually based on the observed signal spectrum , or equivalently, the estimation of the coefficients .
4. Wideband Parallel Compressive Spectrum Sensing
Wideband spectrum sensing is composed of several crucial steps: first, spectrum estimation; second, calculate the sufficient statistics, during which digital signal processing is needed to improve the front-end sensing sensitivity by processing gain and identification of the primary users based on knowledge of the signal characteristics ; last, to decide whether there exist primary users based on the sufficient statistics. Here we focus on the wideband spectrum estimation step, that is, estimating the unknown coefficients in (5).
4.1. Mixed-Signal Compressive Sensing Architecture
The parallel segmented compressive sensing (PSCS) structure is shown in Figure 2, which we first proposed in . For the completeness of this paper, in this section we recap how the analog compressive sensing at sub-Nyquist rate is realized via the PSCS architecture.
In the PSCS architecture, the input signal is sent to parallel paths. In the path, is mixed with a random basis function . A good choice for the random basis is to use PN (Pseudonoise) sequences because they can be conveniently generated by digital logic circuits. The output of the mixer is then sent to a sliding window with a width of and integrated. Two adjacent windows have an overlapping time , which defines an overlapping percentage , as shown in Figure 3. The output of the integrators is sampled and samples are collected at each path. The sample of the branch is given by
There are a total of samples collected every seconds and these samples are organized into a vector as follows:
where is the vector consisting of the samples from all branches.
Similarly, we can calculate the reconstruction matrix . The element at the row and the column is given by
Therefore, we have . Then, we can estimate by solving the problem in (1) and reconstruct the original signal using .
4.2. A Wideband Spectrum Sensing Example
To show the effectiveness of the proposed wideband PSCS architecture we present a simulation, where the input signal is modeled as a frequency-domain sparse multi-carrier signal as given in (5). The mixed-signal compressive sensing based on the PSCS architecture given in Figure 2 is used for spectrum estimation. The sampling rate reduction is measured by the Normalized Sampling Rate (NSR), which is defined as
where is the sampling rate required using the PSCS and is the corresponding Nyquist sampling rate. The signal reconstruction quality is evaluated by the normalized Mean Square Error (MSE), which is equal to
In the simulation, the input signal to the PSCS architecture is assumed to be a 17-sparse frequency-domain multi-carrier signal with 128 subcarriers, that is, and . There are 5 primary bands with an overall bandwidth of MHz. The subcarrier spacing and the primary user's frequencies are , MHz. The input power dynamic range of the primary users is 15 dB. dB, where is the total signal power over the whole bandwidth divided by the total noise power over the whole bandwidth. (Note how noisy the received signal is in this example, shown in Figure 4.) In Figures 4 and 5, from top to bottom, the four plots represent the primary transmitted signal, the received primary users' signal at the sensing radio, the reconstructed signal from the time-domain samples via the Nyquist rate ADC, and the reconstructed signal from the transform-domain samples via mixed-CS at an NSR of . The measured for the two reconstructed signals is dB and dB, respectively. Note that even with a lower sampling rate, the sensing radio based on mixed-signal PSCS is more robust against noise than the traditional digital approach based on the DFT, because CS takes advantage of the knowledge of the signal structure and its sparsity.
5. Flexible Spur Rejection via the Overlapping Windowed Integration
In addition to the capability of sensing and reconstructing sparse signals at sub-Nqyuist rate, the PSCS architecture has many special characteristics. For example, the parallel architecture gives a design tradeoff between the sampling rate and the system complexity . In this section, we focus on the PSCS architecture's spurious frequency rejection schemes. Since one critical type of spur in the PSCS architecture is the leakage of the clocks for the PN generators to the integrator, as illustrated in Figure 6, we will focus on this particular type of spur in this section, although the rejection scheme applies more generally.
Recall that in Figure 2, the output after the mixer is sent to a sliding window with a width of and integrated over seconds, and there is an overlap time of between two adjacent windows as illustrated in Figure 3. The integrator, with a reset every seconds, provides a simple realization of a type lowpass filter with nulls at frequencies of , where . By setting the random generator clock frequency equal to a harmonic of the reset frequency, the nulls coincide with spur frequencies from the random generator clock and so filters them, where the overlapping scheme provides the flexibility on setting the locations of the nulls. In some cases, without the overlapping scheme, the objective of setting the clock frequency on the nulls of the sinc type lowpass filter may conflict with the sampling rate requirement which is determined by the signal's sparsity. In order to show this, consider the following example.
Let the input signal to the PSCS architecture be a 19-sparse frequency-domain multi-carrier signal with 128 subcarriers, that is, and , which corresponds to a sparsity of 15%. The subcarrier spacing is and the symbol duration time is nanoseconds. The locations of the active subcarriers are chosen randomly and changed every seconds. According to simulation results, the minimum NSR is for this parameter setup. Equivalently speaking, 72 samples are needed per 128ns to reconstruct the signal perfectly. Using two parallel paths, 36 samples are collected every 128 nanoseconds at each path, that is, and . With this parameter setup and without the overlapping scheme, , , and the nulls of the sinc type lowpass filter occur at .
There may exist some leakage into the integrators from the clock signal, as illustrated in Figure 6. According to the CS theory, the clock frequency is usually at the Nyquist frequency where in this example. Because , the spurs due to the clock leakages will fall near the 3rd sidelobe's peak of the sinc type lowpass filter and bring distortion to the reconstructed signal. With the overlapping scheme, we can choose and by introducing an overlapping ratio of 11.43%, then and the spurs due to the clock leakage can be filtered (considering the clock resolution requirement, an overlapping ratio of 11.25% is suggested in practice.). Based on Figure 3, this can be mathematically expressed as
According to (14), given a desired sampling rate, or equivalently speaking, a specific , varying will change the relative location of the leakage frequency to the filter nulls, as illustrated in Figure 7.
Note that if we do not want to introduce any overlapping but still wish to null out the clock leakage, the only option in the above example is to increase the sampling rate and make an integer no less than . By introducing a nonzero , we can conveniently make an integer without increasing the sampling rate.
Figure 8 shows the MSE of the reconstructed signal versus the overlapping ratio when there is some clock leakage into the integrators. Note that in the simulation the amplitude of each subcarrier is set to 1. Since , the signal's peak amplitude is 19. Allowing a 10 dB margin to account for the multi-carrier signal's large peak-to-average ratio, the clock leakage with an amplitude of 0.1 (0.4) is roughly 35 dB (23 dB) below the signal's average power. As shown in Figure 8, the flexibility of setting the null frequencies by the overlapping scheme can bring about 20 dB gain after filtering the spurs due to the clock leakage.
Note also that the overlap in the integration windows provides wider filter nulls than the sinc filter. Because of the existence of the phase noise on the clock signal in practice, even if we can set the clock on the null frequency, it is inevitable that remains some leakage due to the widening of the spurs spectrum. The wider nulls provides the possibility of further improving the harmonic rejection when the phase noise is significant.
6. Low-Speed Off-the-Shelf Component Prototype
As a proof of concept, we built a low-speed prototype using off-the-shelf components, where the input signal is a real BPSK modulated multi-carrier signal with 4 active subcarriers and the active subcarriers hop over the frequencies KHz every microseconds. Considering the system complexity, we employed 4 parallel paths for the prototype. Simulation shows that the signal can be reconstructed perfectly when each parallel path produces 16 samples every microseconds, which corresponds to 32% of the Nyquist sampling rate.
6.1. Overall Configuration
The overall configuration of the prototype is shown in Figure 9, where the digital part is responsible for generating the input sparse signal, the triggering signal, the pseudorandom basis, and the clock. The analog part is used to realize the random basis projection that is essential for the signal reconstruction. The built-in ADC in the oscilloscope is used to collect the sampled data. Then, the collected data is sent to a PC and processed via Matlab code to reconstruct the signal. In the following sections, each building block will be introduced in detail.
6.2. Multicarrier Signal Generator
An Agilent 33120A arbitrary waveform generator is used to generate the input multitone sparse signal. Specifically, the multitone signal is programmed in the PC first and then downloaded into the wave generator. The output port of the generator is triggered by the microcontroller in order to synchronize with the integrator clock that is also generated by the microcontroller.
6.3. Mixers and Integrators
Figure 10 depicts the macromodel of one path in the prototype. As shown, the input signal is first translated into current by the OTA and then mixed with the pseudorandom signal. After mixing, the signal is integrated in the sampling capacitor with a timing window. In the sampling circuit the interleaving capacitor is employed. Finally the ADC yields digital output data. The OTA we employed is a TIOPA861 with Gm of 116mS and all the switches are implemented with transmission gate CD4066BCN.
The pseudorandom number (PN) is or 1, whose spectrum is a sinc function. The main lobe is from 0 to , where is the clock period of the PN generator. In our test bed is . After the mixing, the signal is shaped by the embedded lowpass filter provided by the integration window. The frequency response of the LPF is a sinc function. The main lobe spans , where is the integration time. In our test bed the is roughly 30 KHz.
The random projection of the input analog signals is realized with mixers and integrators. Figure 11 gives the circuit implementation of one parallel path and Figure 12 gives the corresponding pin connection relationship for the integrator. The transconductance amplifier ( stage) translates the signal voltage into current, which can be easily mixed with the pseudorandom numbers (1/1) by the following passive switch mixer. After mixing, the signal is integrated with an overlapping window and then sampled by the ADC in each path. The circuit is built up differentially so that the system is more robust to supply noise, clock jitter, and even-order harmonics. The double balanced passive mixer does not introduce significant noise and distortions.
At each path, the mixer consists of transmission-gate switches controlled by PN sequences. The PN sequence is implemented with a linear feedback shift register (LFSR). In our prototype, the clock frequency is chosen to be 1 MHz, which is higher than the Nyquist sampling rate. Because the PN sequences are repeated every and there are 4 parallel paths, we need 4 independent PN sequences with a length of 500. An 11-bit LFSR is used to generate a PN sequence with a length of 2047 and then divided into 4 segments. As a check, the autocorrelation function of the PN sequences is calculated to make sure that the four PN sequences are incoherent.
An overlapped time-interleaving charge-domain sampling integrator is chosen for the analog path. The integrator schematic is shown in Figure 13, and are two integration switches for the left and right branches, respectively. and are readout switches; and are reset switches. By utilizing these six switches combined with the two integration capacitors and , according to the clock diagram shown in Figure 14, we can realize a conventional time-interleaving charge-domain integrator without overlapping. Time interleaving means when the left branch is integrating while the right is reading out, and vice versa. By doing this, a complete sampling of the signal is achieved. In addition to time interleaving, a small overlapping time is introduced by one more capacitor and two control switches and .
As shown in Figure 14, phase1 and phase3 are to realize the overlapping through charge redistribution and sharing, and phase2 and phase4 are the readout times for the right and the left branches, respectively. During phase1, the input current charges both and while is idle. Since all capacitors have the same value, the current splits equally by half into both capacitors. In the succeeding phase, is switch-connected to and readout together, so that is integrating for the right branch during phase1. Equivalently, as shown in the timing window diagram, the window splits by half during the overlapping time. The key point here is that both branches are integrating and no data is readout during window overlapping times.
Note that the overlapping windowing realized using the circuit in Figure 13 is somewhat different from the overlapping windowing in Figure 3, as shown in Figure 15. In Figure 3, the charges accumulated during the current window period include 100% of the charges from the last seconds of the previous windowing period but no charges from the next windowing period. In Figure 13, the charges accumulated during the current windowing period include 50% of the charges from both the last seconds of the previous windowing period and the first seconds of the next windowing period, which is more realistic from the implementation perspective.
6.4. Data Collection and Signal Reconstruction
For simplicity, we use the inherent ADC of the oscilloscope (Tectronix TDS 3054 500 MHz, 5 Gs/s) to sample the output of the integrators. The sampled data is transferred to the PC via the GBIP port. With the collected samples, the signal is reconstructed as described in Section 2.
6.5. Dealing with Circuit Nonidealities
While implementing the prototype, it is inevitable that the system has some nonidealities such as the delay caused by each component, the gain variation, and the mismatch among parallel paths. Considering all the nonideal factors, the actual relationship between the collected samples and the coefficients becomes
where the element at the row and the column of is given by
Here, and reflects the timing error on the slicing window, reflects the frequency offset, and reflects the gain and phase mismatches, and the reflects the error of the random basis which could be attributed to the jitter and nonzero response time.
Because the actual relationship between and is given by (15), we need to replace with in (1) when estimating ; otherwise, some extra error will be introduced. In , the authors discussed the impact of some circuit imperfections, such as the finite settling time of the PN sequences, and the timing uncertainty, and a background calibration algorithm based on LMS was proposed to compensate for the error due to these circuit nonideal factors. Because of the complexity of the background calibration, here we use a more simple approach based on direct training to deal with the circuit nonidealities. The direct training approach is illustrated in Figure 16. During the training stage, we inject a single-tone signal one at a time to the prototype and collect the samples from the 4 parallel paths, so that these samples will fill one column of the reconstruction matrix . After sending 100 single-tone signals, we obtain a complete matrix which will be used for signal reconstruction.
This pilot-based method is based on the assumption that the system is linear and time-invariant. Fortunately, our circuit level design ensures that the input signal swing is within the linear range of the system, and the microcontroller ensures that the system has the same initial condition for every run. Therefore, the linear time-variant assumption is reasonable. Implementing the background calibration for circuit imperfection compensation is part of our future work.
6.6. Testing Results
The testing setup for the prototype is shown in Figure 17. A series of experiments are done to test the functionality of the system. Table 1 summarizes the testing results, where and stand for the polarity of the BPSK modulation. Note that we scale the amplitude of each subcarrier according to the number of tones such that the amplitude of the multi-carrier signal is within the dynamic range of the system. From the testing results, the prototype achieves the design specification.
The Parallel Segmented Compressive Sensing (PSCS) front-end is able to sample and reconstruct analog sparse and compressive signals at sub-Nqyuist rate. The overlapping windowed integration in the PSCS front-end provides a spurious frequency rejection scheme by setting the lowpass filter nulls on the spurious frequencies without sacrificing the sampling rate requirement. A low-speed prototype is built with off-the-shelf components, which is able to sense sparse analog signals at sub-Nyquist rate.
The authors acknowledge the contributions of the students, faculty, and sponsors of the Analog and Mixed-Signal Center at the Texas A&M University. This research project was funded under the DARPA Analog-to-Information Receiver Development Program (Army Research Laboratory Cooperative Agreement no. W911NF-08-2-0047) and the Army Research Laboratory Cooperative Technology Alliance (ARL-CTA) contract no. DAAD-19-01-2-0011. Some of the results in this paper were reported in the conference of IEEE ICASSP’08, Las Vegas, Neveda, USA  and IEEE DCAS’09, Dallas, Texas, USA .
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