- About this Journal
- Abstracting and Indexing
- Aims and Scope
- Annual Issues
- Article Processing Charges
- Articles in Press
- Author Guidelines
- Bibliographic Information
- Citations to this Journal
- Contact Information
- Editorial Board
- Editorial Workflow
- Free eTOC Alerts
- Publication Ethics
- Reviewers Acknowledgment
- Submit a Manuscript
- Subscription Information
- Table of Contents
International Journal of Distributed Sensor Networks
Volume 2013 (2013), Article ID 754206, 8 pages
Calibration Techniques for Low-Power Wireless Multiband Transceiver
1Research Center for Mobile Computing, Tsinghua University, Beijing 100084, China
2Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Received 3 August 2012; Revised 2 April 2013; Accepted 4 April 2013
Academic Editor: Lei Zhang
Copyright © 2013 Shouyi Yin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 555–558, May 1998.
- A. Aktas and M. Ismail, “CMOS PLL calibration techniques,” IEEE Circuits and Devices Magazine, vol. 20, no. 5, pp. 6–11, 2004.
- W. B. Wilson, U. K. Moon, K. R. Lakshmikumar, and L. Dai, “CMOS self-calibrating frequency synthesizer,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1437–1444, 2000.
- J. Lee, K. Kim, J. Lee, T. Jang, and S. Cho, “A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13 μm CMOS,” in Proceedings of the IEEE Asian Solid-State Circuits Conference, pp. 67–70, November 2007.
- M. Kondou, A. Matsuda, H. Yamazaki, and O. Kobayashi, “A 0.3 mm2 90-to-770 MHz fractional-N synthesizer for a digital TV tuner,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '10), pp. 248–249, February 2010.
- J. Shin and H. C. Shin, “A 1. 9-3. 8 GHz fractional-N Σ-Δ PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency,” IEEE Journal of Solid-State Conference, vol. 47, pp. 1–8, 2012.
- H. Y. Shih, C. N. Kuo, W. H. Chen, T. Y. Yang, and K. C. Juang, “A 250 MHz 14 dB-NF 73 dB-gain 82 dB-DR analog baseband chain with digital-assisted DC-offset calibration for ultra-wideband,” IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 338–350, 2010.
- Y. Wang, B. Afshar, T. Y. Cheng, V. Gaudet, and A. M. Niknejad, “A 2.5 mW inductorless wideband VGA with dual feedback DC-offset correction in 90 nm CMOS technology,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC '08), pp. 91–94, June 2008.
- Y. Zheng, J. Yan, and Y. P. Xu, “A CMOS VGA with DC offset cancellation for direct-conversion receivers,” IEEE Transactions on Circuits and Systems I, vol. 56, no. 1, pp. 103–113, 2009.
- L. Zhang, H. Jiang, and F. Li, “DC offset calibration method for zero-IF receiver removing the PGA-gain -correla ted offset residue,” AEU-International Journal of Electronics and Communications, vol. 67, no. 7, pp. 578–584, 2013.
- H. I. Lee, J. K. Cho, K. S. Lee et al., “A Σ-Δ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1164–1169, 2004.
- Z. S. Cheng and J. C. Bor, “A CMOS variable gain amplifier with DC offset calibration loop for wireless communications,” in Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT '06), pp. 29–32, April 2007.