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International Journal of Microwave Science and Technology
Volume 2011 (2011), Article ID 452348, 16 pages
Scalable RFCMOS Model for 90 nm Technology
1School of EEE, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798
2Cascade Microtech Inc., Singapore Science Park II, Singapore 117586
3Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
Received 30 May 2011; Revised 8 September 2011; Accepted 12 September 2011
Academic Editor: Mattia Borgarino
Copyright © 2011 Ah Fatt Tong et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper presents the formation of the parasitic components that exist in the RF MOSFET structure during its high-frequency operation. The parasitic components are extracted from the transistor's S-parameter measurement, and its geometry dependence is studied with respect to its layout structure. Physical geometry equations are proposed to represent these parasitic components, and by implementing them into the RF model, a scalable RFCMOS model, that is, valid up to 49.85 GHz is demonstrated. A new verification technique is proposed to verify the quality of the developed scalable RFCMOS model. The proposed technique can shorten the verification time of the scalable RFCMOS model and ensure that the coded scalable model file is error-free and thus more reliable to use.
The relentless scaling down of CMOS technologies has greatly improved the RF performance of MOSFET. It has been reported that for a technology node of 90 nm, high of 209 GHz and of 248 GHz are achieved . Furthermore, the scaling down of the transistor has brought about lower , and it is now comparable to the reported SiGe BJT process [1, 2]. The improved RFCMOS performance coupled with its lower cost has motivated circuit designers to integrate digital, mixed-signal, and RF transceiver blocks into a single chip [3–7]. However, for these RF chips to operate at higher-frequency region, the circuit design specifications will become more stringent, and this will require accurate and scalable RFCMOS models that can be simulated accurately at high-frequency region. Furthermore, by employing scalable RF CMOS model into the process design kit (PDK), the circuit design environment is improved, and this can help circuit designers in their circuit optimization and shorten the design cycle and time to market of these RF chips.
Most of the RF models developed today are based on the macromodelling approach. In this approach, subcircuit components are added to the transistor’s core model to model the RF parasitic of MOSFET structure [8, 9], and the core model used is usually the commercially available models such as BSIM3v3  and BSIM4 . The subcircuit components are extracted from the measured S-parameters of the transistor, but the extracted values of these RF components can differ when different extraction technique is used. All the existing RF parameter extraction technique is based on the transistor’s small-signal equivalent circuit analysis. Therefore, to characterize an RF MOSFET, all its RF parasitic elements must be included into the small-signal equivalent circuit. Although it has been demonstrated that including the subcircuit components into the core model can accurately simulate for the transistor’s RF characteristics, such developed model is normal for discrete transistor sizes. In order to generate a geometry-scalable RFCMOS model, the extracted subcircuit component values must be studied for its geometry dependency and by formulating equations to capture their physical effects at high-frequency region, and a physical scalable RFCMOS model can be generated. Presently, some publications are reported for the scalable RF MOSFET modelling [12–14], but these publications [12, 14] do not show all the geometry-scalable equations of the subcircuit components. In , the formulated equations for the subcircuit components were empirical and have no physical meaning, and furthermore, only one device size of and plot is presented.
In this paper, the geometry dependencies of the RF subcircuit components were studied, and the formulation of these RF components was done based on their physical effects and the geometry of the layout structure. The scalable transistor’s RF characteristics with respect to the layout geometry, biasing, and frequency will be demonstrated with good accuracy between the measured and simulated results. Presently, there is no standard technique proposed for quantifying the quality of a developed scalable RF model. Hence, a new technique is proposed in this paper to help modelling engineers to verify and check the developed scalable RF model for their scalability and accuracy. By utilizing this proposed technique, the model geometry scalability with respect to the transistor’s unit width () and finger number () is monitored to ensure that the formulated geometry equations are correct. Furthermore, by plotting the proposed accuracy plots, the error population of the developed model is monitored and ensured that they are below the error’s specification of the developed model. The scalable RF model was developed for 90 nm process with channel length of 70 nm for a frequency range of 50 MHz to 49.85 GHz. The devices under test (DUT) are NMOS transistors with of 4, 8, 16, 24, 32, 48, and 64 and of 1, 2.5, and 5 μm. By studying the geometry dependence of the RF subcircuit components for the above DUT, the physical geometry equations with fabrication process parameters are formulated, and from the comparison between the extracted and calculated component values, excellent agreement for all the above combinations of and is shown.
Section 2 shows the transistor’s equivalent subcircuit model and the layout of the DUT used. The detailed explanation on the formulation of the equation for the subcircuit components is then shown, and the plots to compare between the calculated and extracted component values are presented. In Section 3, the good fitting between the measured and simulated DC and RF results for the various geometry combinations is shown, and the further verification with the proposed technique for the generated scalable RFCMOS model is presented. The conclusion follows in Section 4.
2. Scalable RF MOSFET Modelling
Figure 1 shows the proposed RF equivalent subcircuit model. All the subcircuit components are physical and can be used for transistor that has the source and body terminal tied together and grounded.
The resistance represents the effective lumped gate resistance that consists of both the electrode resistance and the distributed channel resistance . The resistances and represent the effective source and drain resistance that consist of the metal line, via, and contact resistances.
The capacitances and represent the effective gate-to-source and gate-to-drain capacitances and consist of both the overlap and fringing capacitances between the terminals. represents the drain-to-source fringing capacitance between the metal lines that connect to the source and drain diffusions. As the internal junction capacitances of the core model are turned off, the external diodes , , , and are added as the junction capacitances to connect the substrate resistance network. stands for the area intensive diode, while the stands for the perimeter intensive diode, and the definition is the same for the source-to-body junction diodes. The parameters , and represent the substrate network resistances. Finally, and are defined as the gate-to-substrate capacitance and resistance over the shallow trench isolation (STI) region.
Figure 2 shows the simplified layout of the RF NMOS transistor. The transistor has a multifinger configuration with double-contacted gate polystructure. Dummy gate poly is added to improve the gate structure formation. The metal 1 and metal 2 are used for the connection of the gate terminal. The source diffusions are connected using the metal 1 and shortened to the body terminal or P-well, while the drain diffusions are pulled out using the metal 3.
In order to extract physical subcircuit components in the macromodel, all the physical layers and their geometry that are used to form the structure of the transistor must be known. The extraction technique used to extract the subcircuit components values is as shown in .
2.1. Gate Resistance Modelling
Figure 3 shows the simplified polysilicon gate structure and its distributed parasitic resistances. At RF frequency region, is influenced by three physical effects. The three effects are the distributed gate electrode resistance, the non-quasi-static (NQS) effect in the channel [15, 17], and the polysilicon gate extension out of the active region follows: In , the distributed effect of the gate electrode has been studied and the following equations have been derived to calculate the distributed gate electrode resistance. In (2) and (3), the variable is the number of fingers, is the gate sheet resistance, and and are the channel length and unit width of a single finger. The factors of 1/3 and 1/12 are used in (2) and (3) to account for the distributed gate resistance effect and the different gate connection configuration at the ends of the gate structure.
The polysilicon gate extension as shown in Figure 1 contributes to the total gate resistance as follows: At RF frequency region, the channel will become like a distributed RC network as shown in Figure 1. The distributed channel resistance will reflect to the gate through the capacitance network and increase the total gate resistance. Note that this NQS channel resistance is bias and geometry dependent. However, it is reported that a simple gate resistance can model the distributed gate resistance effect, and it is accurate up to for an MOSFET without any significant NQS effects . Hence, only a geometry-dependent NQS channel resistance is assumed to contribute to the total gate resistance as follows: Note that the variable is defined as a factor of the channel sheet resistance that is reflected back to the gate structure.
Figure 4 shows the comparison between the extracted and calculated versus and plots. It is observed that is inversely proportional to , and there exists a minimum at the of 2.5 μm. The and dependence of can be explained by considering (1)–(5). From (2)–(5), the three physical effects on the gate resistance are inversely proportional to , and this explains the trend of versus . As shown in (3), the resistance is directly proportional to , but in (5), the resistance is inversely proportional to . The effect on the resistance and will compete with each other and cause to have a minimum point as shown in Figure 4. Therefore, based on the proposed physical geometry equation, the calculated and extracted resistance matches well with the change in and of the transistor.
2.2. Source and Drain Resistance Modelling
The resistances and shown in Figure 1 are defined as the effective resistances that consist of the metal line, via, and contact resistances as shown in the layout of Figure 5. It is assumed that the source and drain resistance model in the BSIM3v3 model only models the active region of the parasitic resistances. Based on the above layout, the following equations can be derived to represent and : The variables and represent the sheet resistance for metal 1 and metal 3, and the variables , , and represent the contact, via1, and via2 resistances and the , , and are the numbers of contacts and source and drain diffusions in the transistor.
Figure 6 shows the comparison between the extracted and calculated and versus plots. It is observed that both resistances are inversely proportional to , and there exists a minimum point of resistance value at the of 2.5 μm. From (6), the and are the number of source and drain diffusions, and they are proportional to . Hence, the and resistances show the inverse proportionality with . From Figure 5, the variables , and are proportional to the of the transistor, and when they are applied to (6), the effect on both and will compete with and cause a minimum resistance level to occur at of 2.5 μm.
2.3. Gate-to-Substrate Capacitance and Resistance Modelling
The components and that are shown in Figure 1 are defined as the gate-to-substrate capacitance and resistance over the STI region, and they are shown in the cross-sectional structure in Figure 7. The dotted enclosed region in Figure 7 is the gate area that is on top of the STI region generating the parasitic components and , and based on the above layout geometry, the following equations are formulated: The variables and are the parasitic capacitances per unit area of metal 1 and metal 2 over the STI region, while the variables and are the area of the dotted enclosed region of metal 1 and metal 2 as shown in Figure 7. From (7), it is shown that is mainly contributed by the parasitic capacitances due to the layers of gate metal 1 and metal 2 over the STI region. The extracted variables and in (7) represent the capacitance per unit area (fF/μm2) of the enclosed metal 1 and metal 2 regions as shown in Figure 7. As the dielectric thickness between metal 2 and the substrate is higher than that of metal 1, it is expected that the extracted is higher than . Since there is some area under the enclosed metal 1 and metal 2 regions that is overlapped with the polysilicon gate, the proposed equation (7) may overestimate slightly, and a small capacitance may be required to be subtracted from the above equation.
and are extracted using Seneca and Substrate storms  that simulate the layout structure as shown in Figure 7. Based on the extracted results of , it is found that it is only dependent on , and it is formulated as shown in (8). Note that the extracted is defined as the substrate parasitic resistance under the STI region.
Figure 8 shows the comparison between the extracted and calculated and versus plots. It is observed that is proportional to while is inversely proportional to . In (7), is dependent on and, and when increases, the two areas will increase and cause to increase.
Based on the layout structure in Figure 7, it is observed that the length of is proportional to . By using the simple resistance equation that uses the sheet resistance multiply with the number of squares, it is obvious that the number of squares in the signal flow path of is inversely proportional to the length of . Hence, will decrease with increasing .
2.4. Gate-to-Source and Gate-to-Drain Capacitances Modelling
The capacitance and in Figure 1 represent the overlap and fringing capacitances between the gate-to-source and gate-to-drain terminals as shown in Figure 9. Based on the above layout structure, it is obvious that the amount of overlap capacitance is dependent on the number of source and drain metal lines that overlap the gate metal, while the fringing capacitances will be dependent on the separation distance between the source/drain metal lines to gate polysilicon structure and the of the transistor. Since the separation distance between the source/drain metal lines and the gate polysilicon structure is fixed, therefore the fringing capacitance is only dependent on transistor’s . Based on the above analysis, the following equations are formulated: Note that is the overlap capacitance between the gate (metal 2) and source (metal 1) metal lines, and is the fringing capacitance between the gate structure (polysilicon) and the source (metal 1) metal lines. Here is the overlap capacitance between the gate (metal 1) and drain (metal 3) metal lines and is the fringing capacitance between the gate structure (polysilicon) and the drain (metal 1) metal lines. It is assumed that the fringing capacitances from the metal 2 and metal 3 lines of the drain metal structure to the polysilicon gate are small and negligible when compared to the metal 1 and to the polysilicon gate fringing capacitance.
As the dielectric separation distance between the metal 3 (drain) and metal 1 (gate) is larger than the case of metal 2 (gate) and metal 1 (source), it is expected that will be larger than . Furthermore, the extracted must be close to the extracted or slightly smaller.
Figure 10 shows the comparison between the extracted and calculated and versus plots. It is observed that both capacitances are proportional to and , and the extracted capacitance is slightly larger than . In (9) and (10), the dependence in both of the capacitances is due to the variables and , and since has one more diffusion than the , the extracted capacitance is slightly larger than . The dependence as shown in Figure 10 is mainly due to the fringing capacitance effect in (9) and (10).
2.5. Drain-to-Source Capacitance Modelling
is defined as the fringing capacitance between the metal lines that connect the source and drain diffusions. The location of the fringing capacitance is indicated in Figure 11(a) that uses the cross-section view of A-A′ in Figure 9. Based on the layout structure, it is predicted that the fringing capacitance is proportional to and of the transistor. Hence, the following equation is formulated for : Note that is the fringing capacitance per unit width between the metal lines of the source and drain metal structures.
In Figure 11(b), the comparison between the extracted and calculated shows that the proposed formulated equation can accurately predict the change in and .
2.6. Substrate Resistances Modelling
By using the cross-section view of A-A′ in Figure 9, the substrate resistances network is added into the structure to indicate the location of the parasitic as shown in Figure 12. and are junction capacitances that are replaced by the junction diodes as shown in Figure 1. and represent the substrate resistances under the channel, while connects the intrinsic bulk node to the body terminal. Based on the layout structure, it is predicted that and are proportional to , while is inversely proportional . Hence, the following equations are formulated for the substrate resistances: In (12), the variable is the substrate resistivity and has the unit of Ω μm, and is the substrate sheet resistance under the active region and has the unit of Ω/number of square. The parameter represents the source and drain junction depth, and its value can be found in the BSIM3v3 model parameters.
3. Measurement Results and Discussion
3.1. Modelling Results
The devices under test (DUT) are thin gate NMOSs with fixed of 70 nm, of 1, 2.5, and 5 μm, and of 4, 8, 16, 24, 32, 48, and 64. The S-parameters were measured using the HP8510 network analyzer with GSG RF probes for a frequency range from 50 MHz to 49.85 GHz at the various bias combinations of the gate-to-source and drain-to-source potentials. After the system calibration was performed using LRRM technique, the RF transistor and its deembedding structures were measured. In this measurement, the standard open and short deembedding structures were used to remove the pad and interconnects parasitic .
In order to demonstrate the scalability of the RF model, measured and simulated DC, Y-parameters, and plots are presented in this section. Figures 14–16 show the measured and simulated results for fixed of 1 μm with varying of 8, 24, and 64 at the biasing combination of and ranging from 0.3 to 1.2 V. From the comparison between the measured and simulated results, it is observed that the RF model can accurately predict the measured results as varies. The scalability of the RF model is demonstrated in Figures 15, 17, and 18 for fixed of 24 with varying of 1, 2.5, and 5 μm. Hence, from Figures 14–18, the proposed RF model is shown to be geometry scalable for and for the frequency range from 50 MHz to 49.85 GHz.
3.2. Further Verification with Proposed Technique for the Scalable Model
In a scalable RFCMOS model, there are many different variables that determined the scalability of the RF model. It becomes very tedious to verify and monitor the model accuracy further so that the developed model, file has to be scalable for a certain range of geometry, biasing and frequency variables. Hence, a new verification technique is proposed in this paper. This proposed verification technique is crucial to both the modelling engineers and the model file end users as it helps them to monitor the quality of the developed model and at the same time, the model file can be checked for any errors in the coded geometry equations of the parasitic subcircuit components. Furthermore, by using this proposed technique, the amount of verification time required to check the developed model file is reduced, and thus reducing the overall model development time.
Figure 19 shows the model accuracy plots for NMOS transistors with different of 4, 8, 16, 24, 32, 48, and 64 and of 1, 2.5, and 5 μm extracted at V and V. From the box plots, it is observed that 10 to 90% of the error population from the DC, S-parameters, and Ft are within ±10%. In the three plots, the model accuracy for all the fabricated devices is monitored at DC, 2.45, 5.45, and 10.25 GHz. Therefore, by generating such model accuracy plots, the quality of the developed RF model in terms of its accuracy is monitored for all the fabricated device sizes and at the different frequency points. Furthermore, by plotting at the other biasing points, the model accuracy of the RF model can be checked for those important biasing regions.
Figure 20 shows the model continuity plots for the parameters and versus different and of 1, 2.5, and 5 μm extracted at V and V. From the three plots, it is observed that the simulated (blue line) and (red line) overlap each other, and this observation implies that the RF model is continuous from DC to RF region. Furthermore, the simulated transistor’s gain (red and blue lines) can accurately predict the measured data (red and blue symbols) as the and changes and their calculated absolute errors are within the error specification of ±10%. It is also observed that the simulated and scale linearly with for all the three . By plotting such model continuity plots at other biasing points, the , , and biasing effect on the RF model are monitored at both the DC and low-frequency region. In the case when the coded equations of the subcircuit components in the model file are incorrect, the model accuracy and continuity plots will immediately reflect the incorrect effects of the wrong equations, and this will alert the modelling engineer to check the coded model file again.
In this proposed technique, the model accuracy and continuity plots are generated to monitor the device geometry, biasing, and frequency variables of the RF model. From these two types of plots, the quality of the developed model and the coded model file will be inspected, and the final verified model file will be error-free and reliable to use.
The proposed model accuracy and continuity plots can also be used as one of the model acceptance criteria, whereby its accuracy and continuity can be checked before accepting and using the developed RF model file.
In this paper, the physical formation of the subcircuit parasitic is discussed with respect to its layout structure. The scaling effect of the device geometry is accounted for in the proposed scalable equations for each of the parasitic components. By implementing the proposed scalable equations for the parasitic components into the conventional subcircuit RF model, a scalable RFCMOS subcircuit model can be generated and shown to be valid up to 49.85 GHz. By using the proposed verification technique, the time required to verify a scalable RFCMOS model can be reduced greatly, and the verification step can also ensure that the developed model is error-free, and therefore, it is more robust and reliable to use. Although the scalable RFCMOS model can accurately predict the DC and RF characteristics of the transistor it will still require being able to predict its high-frequency noise. Hence, the scalable RFCMOS model will form the base of the RF transistor modelling so that the study of the scalable high-frequency noise modelling can be embarked on to achieve a fully scalable RFCMOS model.
The authors would like to thank K. Takeshita, M. Yano, M. Abe, A. Nakamura, A. Kuranouchi, and S. Tonegawa from Sony for their helpful discussions and valuable inputs.
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