An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="180216.fig.001a" src="https://static.hindawi.com/articles/ijrc/volume-2008/180216/figures/180216.fig.001a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Bug fixing</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="180216.fig.001b" src="https://static.hindawi.com/articles/ijrc/volume-2008/180216/figures/180216.fig.001b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Avoidance of
high volume</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="180216.fig.001c" src="https://static.hindawi.com/articles/ijrc/volume-2008/180216/figures/180216.fig.001c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>Version upgrade</td></tr></table></td></tr><tr class="fig-image" id="d"><td><img alt="180216.fig.001d" src="https://static.hindawi.com/articles/ijrc/volume-2008/180216/figures/180216.fig.001d.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(d) </b>Multiple mode/specfication</td></tr></table></td></tr></table>

<table>The use of a VGLC as a reconfigurable logic core.</table>

International Journal of Reconfigurable Computing

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Figure 1

Figure 1: An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture 