International Journal of Reconfigurable Computing
Volume 2008 (2008), Article ID 736203, 10 pages
doi:10.1155/2008/736203
Research Article

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Chi Wai Yu,1 Julien Lamoureux,2 Steven J. E. Wilton,2 Philip H. W. Leong,3 and Wayne Luk1

1Department of Computing, Imperial College London, London SW7 2AZ, UK
2Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, V6T1Z4, Canada
3Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong

Received 7 July 2008; Accepted 30 October 2008

Academic Editor: Gustavo Sutter

Copyright © 2008 Chi Wai Yu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.