The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="736203.fig.005a" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.005a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>CLBs  connect to one side of EB with highest I/O denisty</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="736203.fig.005b" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.005b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>CLBs  connect to two sides of EB</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="736203.fig.005c" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.005c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>CLBs  connect to three sides of EB</td></tr></table></td></tr><tr class="fig-image" id="d"><td><img alt="736203.fig.005d" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.005d.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(d) </b>CLBs  connect to four sides of EB with lowest I/O denisty</td></tr></table></td></tr></table>

<table>Different pin positions in EB.</table>

International Journal of Reconfigurable Computing

fig5

Figure 5

Figure 5: The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units 