International Journal of Reconfigurable Computing
Volume 2008 (2008), Article ID 901328, 10 pages
doi:10.1155/2008/901328
Research Article

Dynamic Hardware Development

Stephen Craven1 and Peter Athanas2

1Department of Electrical Engineering, The University of Tennessee at Chattanooga, Chattanooga, TN 37403, USA
2Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic and State University, Blacksburg, VA 24061, USA

Received 31 March 2008; Accepted 12 August 2008

Academic Editor: Michael Hubner

Copyright © 2008 Stephen Craven and Peter Athanas. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them. While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design requires developers to work at a low level and contend with many poorly documented architecture-specific aspects. This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high-level synthesis tool to enable the design, simulation, and implementation of dynamically reconfigurable hardware solely from a specification written in C. Unlike previous attempts, this approach encompasses the entirety of design and implementation, enables self-re-configuration through an embedded controller, and inherently handles partial reconfiguration. Benchmarking numbers are provided, which validate the productivity enhancements this approach provides.