Dynamic Hardware Development

Table 1

Previous PR development environments.

Project	Design entry	Model of computation	Architecture	Limitations
Janus	JHDL	Unspecified	Host + FPGA	No partial reconfiguration
				Requires host
SPARCS	Behavioral HDL	Dataflow	Host + FPGA	Requires macro library
				No partial reconfiguration
PaDReH	Multiple	Undefined	Standalone	Few defined tools
Model-Integrated	Dataflow graph	Dataflow	Independent	No partial reconfiguration
				Requires model library
RCAF	JHDL	Unspecified	Host + FPGA	No partial reconfiguration
				Requires host
				Few abstractions
Imperial College	RT-C	Dataflow	Limited by JBits	Requires host
				Manual translation
Caronte	Various	Coprocessor	Embedded proc	Limited automation