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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2009
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Article
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Tab 3
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Research Article
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications
Table 3
PE performances and hardware requirements.
PE
Logic resources
Clock frequency (MHz)
Slice FF
413 (1%)
4-input LUT
3431 (1.5%)
55