Research Article
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications
Table 4
Throughput and hardware requirements for representative DFT circuits.
| | Slice FF | 4-Input LUT | Throughput(Gbps) |
| 9 | 15706 (7.6%) | 61821 (29.8%) | 11.88 | 10 | 14717 (7.1%) | 58031 (28%) | 13.2 | 12 | 8612 (4.2%) | 28383 (13.7%) | 15.84 | 16 | 15706 (7.6%) | 61821 (29.8%) | 21.12 |
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