]>Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs : Algorithm 3
Input: 𝑎 , 𝑏 , 𝑐 ( 1 / 2 , 1 / 2 ) , uniformly distributed
Output: 𝑑
( 1 ) while true do
( 2 )Get new value of 𝑎 , 𝑏 , and 𝑐
( 3 ) 𝑚 1 = 𝑎 2 . 3 8 4
( 4 ) 𝑚 2 = 𝑏 0 . 0 0 3 6
( 5 ) 𝑠 1 = 𝑚 1 + 𝑚 2
( 6 ) 𝑠 2 = 𝑠 1 + 𝑐
( 7 ) New value of output: 𝑑 = 𝑠 2
( 8 ) end while
Algorithm 3: Case study.