]>Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs : Figure 7
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(a) I I R 4 , 𝜎 2 = 1 0 − 3
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(b) I I R 4 , 𝜎 2 = 1 0 − 3 , 𝜆 = 1 7
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(c) F I R 8 , 𝜎 2 = 1 0 − 4
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(d) F I R 8 , 𝜎 2 = 1 0 − 4 , 𝜆 = 8
Figure 7: UWL versus MWL: homogeneous implementations (II).