]>Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs : Table 6
Table 6: Complete versus simplified cost estimation: area improvement (%).

Arch. Bench. Area improvement
MinMaxMean

HOM I T U 0.00 0.95 0.30
L A T 3 0.71 3.50 1.53
I I R 4 0.00 5.35 1.26
F I R 8 0.00 1.77 0.31

HET I T U 0.00 25.85 1.89
L A T 3 1.15 5.77 2.52
I I R 4 0.00 35.57 8.09
F I R 8 0.00 8.11 0.83

All0.0035.57 2.09