A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors
Figure 2
Examples of workload interaction with cache memories and interconnection network; (a) The Impact of cache size on the amount of cache-to-cache transfers; (b) the impact of the number of active cores on the interconnect conflicts; (c) The impact of the number of utilized threads on interconnect conflicts; (d) L2 misses of two concurrently running applications.
