A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="205852.fig.009a" src="https://static.hindawi.com/articles/ijrc/volume-2010/205852/figures/205852.fig.009a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Switch Box</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="205852.fig.009b" src="https://static.hindawi.com/articles/ijrc/volume-2010/205852/figures/205852.fig.009b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Two different behaviors of modified queues</td></tr></table></td></tr></table>

<table>Two major components used for reconfigurable logic between clusters.</table>

International Journal of Reconfigurable Computing

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Figure 9

Figure 9: A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors 