Research Article

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

Table 2

Post-place & route results for decimal fixed-point multiplier with CPA output.

No. of pipeline stages longest path delay [ns] max. freq. [MHz] No. of LUT [ns] latency

0 17.96 57 6557 17.96
1 10.56 95 5916 21.12
2 7.98 125 5385 23.94
3 5.97 167 6074 23.88
4 5.48 183 6237 27.40
5 4.79 209 6402 28.74
6 4.38 229 5576 30.66
7 4.52 221 5574 36.16
8 4.37 229 5576 39.33
9 4.48 224 5610 44.80
10 4.28 234 6139 47.08
11 4.47 224 6283 53.64
12 4.47 224 6318 58.11
13 4.48 224 6520 62.72