Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

Figure 4

FPGA portion of the extended traversal cache framework with unrolled datapaths, each provided with separate traversals through selectively enabled rd_valid[i] signals. Element membership in each traversal is determined by application-specific logic, generator kernels, as part of each datapath (shown here as a dotted segment) and typically data structure-specific logic in the traversal generator, shown here as part of the controller.