Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

Algorithm 1

Modified CSE algorithm to reduce area: The divisors are generated for a set of expressions and the one with the greatest value is extracted. Then the common subexpressions can be extracted and a new list of terms is generated. The iterative algorithm continues with generating new divisors from the new terms, and add them to the dynamic list of divisors. The algorithm stops when there is no valuable divisor remaining in the set of divisors

ReduceArea( {𝑃_𝑖} )

{

{𝑃_𝑖} = Set of expressions in polynomial form;

{𝐷} = Set of divisors = 𝜑;

//Step 1: Creating divisors and calculating minimum

number of registers required

for each expression P_i in {𝑃_𝑖}

{

{𝐷_new} = FindDivisors(P_i);

Update frequency statistics of divisors in {𝐷};

{𝐷}={𝐷}∪{𝐷_new};

P_i->MinRegisters = Calculate Minimum registers required

for fastest evaluation of P_i;

}

//Step 2: Iterative selection and elimination of best divisor

while (1)

{

Find d = Divisor in {𝐷} with greatest Value;

// Value = Num Additions reduced – Num Registers Added;

if( d == NULL) break;

Rewrite affected expressions in {𝑃_𝑖} using d;

Remove divisors in {𝐷} that have become invalid;

Update frequency statistics of affected divisors;

{𝐷_new} = Set of new divisors from new terms added

 by division;

 {𝐷} = {𝐷}∪{𝐷_new};

}

}