Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

<table>Reduction in resources for add and shift method (this paper) relative to that for DA showing an average reduction of 58.7% in the number of LUTs, and 25% reduction in the number of slices and FFs.</table>

International Journal of Reconfigurable Computing

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Figure 11

Figure 11: Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs 