Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

<table>High level resource utilization in terms of # adders and registers for various filters using add and shift method (this paper) versus SPIRAL automatic software. SPIRAL shows a saving of 15% in number of adders and 81% in number of registers at the cost of 68% drop in performance.</table>

International Journal of Reconfigurable Computing

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Figure 15

Figure 15: Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs 