Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

Figure 17

Number of routing channels versus filter size for various cost functions discussed in Section 4.3 with 𝑓_𝑥 being the modified CSE algorithm presented in Algorithm 1 and others based on maximizing or minimizing AMC. 𝑓_{𝑥𝑚𝑖𝑛} is the best scenario that results in the minimum number of routing channels.