Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
Figure 6
Extracting common subexpression (a) Unoptimized expression trees. (b) Extracting common expression (A + B + C) results in higher cost due to inserting additional synchronizing registers. (c) A more careful extraction of common subexpression (A + B) applied by our modified CSE algorithm results in lower cost.
