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International Journal of Reconfigurable Computing
Volume 2011 (2011), Article ID 425401, 15 pages
http://dx.doi.org/10.1155/2011/425401
Research Article

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

1Lab-STICC/CNRS UMR3192, Université de Bretagne-Sud, Centre de recherche, BP 92116, 56321 Lorient Cedex, France
2Cairn Inria/Irisa, Université de Rennes 1, ENSSAT, 6 rue de Kerampont, BP 80518, 22305 Lannion, France
3Leat/CNRS UMR6071, Université de Nice-Sophia Antipolis, 250 rue Albert Einstein, Bt. 4, 06560 Valbonne, France
4InPixal, Immeuble “Le Germanium”, 80 avenue des Buttes de Cosmes, 35700 Rennes, France

Received 26 November 2010; Revised 23 March 2011; Accepted 25 May 2011

Academic Editor: Koen L. M. Bertels

Copyright © 2011 Dominique Blouin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded. Current applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable logic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration. But the dimension introduced in the design of these systems requires more abstraction to manage their complexity and efficient models to provide reliable preliminary estimations. While classical multiprocessor systems can be modeled without difficulty, the use of partial run-time reconfiguration in heterogeneous flexible system-on-chips is generally not covered. The contribution of this paper is to address this with an extension of the AADL language able to model the reconfigurable logic, possibly considering dynamic reconfiguration and power consumption requirements. The proposed AADL model is divided into three levels to provide a generic and hierarchical approach separating the static and dynamic parts of current FPGAs. These levels are exposed in detail and illustrated on a concrete example of FPGA device. The design space exploration of an application deployment using this model is also presented.