AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

Table 2

Example of possible combinations of task allocations within the execution platform when considering that the processor is always active even if no software task have to be executed. Note that the first and last rows are those which are not acceptable due to the total task execution delays (𝑇>𝑃𝑝) or the total task areas (𝐴ℎ>𝐴). Remarks: Conf₁ is incorrect due to the total execution time greater than the period of tasks; Conf₈ is incorrect due to the total area greater than the global area in the reconfigurable space.

Conf.	Task allocation			Software execution			Hardware execution				Global	Global without
	Soft	Hard		Exec Time	Energy		Area	Exec Time	Energy		Exec Time	Low-power mode
												Energy	Av. power
				𝑇𝑠 (tu)	𝐸𝑠 (eu)		𝐴ℎ (cle)	𝑇ℎ (tu)	𝐸ℎ (eu)		𝑇 (tu)	𝐸 (eu)	𝑃 (pu)
Conf1	𝑇1, 𝑇2, 𝑇3	—		110	10000		0	0	0		110	10000	91
Conf2	𝑇1, 𝑇2	𝑇3		50	10000		50000	20	5000		50	15000	300
Conf3	𝑇1, 𝑇3	𝑇2		80	10000		40000	12	1800		80	11800	147
Conf4	𝑇2, 𝑇3	𝑇1		90	10000		30000	10	1000		90	11000	122
Conf5	𝑇1	𝑇2, 𝑇3		20	10000		90000	20	6800		20	16800	840
Conf6	𝑇2	𝑇1, 𝑇3		30	10000		80000	20	6000		30	16000	533
Conf7	𝑇3	𝑇1, 𝑇2		60	10000		70000	12	2800		60	12800	213
Conf8	—	𝑇1, 𝑇2, 𝑇3		0	10000		120000	20	7800		20	17800	890