Research Article

Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs

Table 2

Implementation results.

CompareXilinx XCV1000 [4]Xilinx XC4VFX12

Slices8884/122885107/5549
LUTs1776810216
Max. clock frequency63.07 MHz100 MHz
Single loop processing time0.17 s~0.07 s