Research Article
A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance
Table 1
Large configuration results.
| | Arch. |
App. | Large Cfg.: 4 tiles, each tile has PEs | | Ops | Cycles | Avg. IPC | Perf. gain | Efficiency |
| | ADRES | idct_row() | — | — | 27.7 | — | 43% | | FDR-CGRA | idct_row() | 857 | 24 | 35.7 | 29% | 56% |
| | ADRES | idct_col() | — | — | 33.0 | — | 52% | | FDR-CGRA | idct_col() | 1185 | 33 | 35.9 | 9% | 56% |
| | FDR-CGRA | Interpolate _avg4_c | 1193 | 40 | 29.8 | — | 47% | | FDR-CGRA | Interpolate _halfpel__c | 1295 | 38 | 34.1 | — | 53% | | FDR-CGRA | sad16_c() | 3441 | 106 | 32.5 | — | 51% |
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