A Protein Sequence Analysis Hardware Accelerator Based on Divergences

Table 3

Area and performance synthesis results.

NO. of PEs	Max. passes	Max. HMM nodes	Max. sequence size	Combinational ALUs	Dedicated registers	Memory bits	% Logic	Max. clock frequency (MHz)
25	25	625	8192	31738	18252	2609152	25	71
50	25	1250	8192	59750	35294	3121152	49	71
75	25	1875	8192	93132	52520	3663152	75	69
85	27	2295	8192	103940	59285	5230592	84	67