Research Article
A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection
Table 1
Synthesis results for Master node components.
| Module | LUT | Reg. bits | BRAM |
| Network core incl. management | 12,297 | 8,884 | 93 | Ring interface | 788 | 1,489 | 16 |
| Mapped incl. MAC, | 16,532 | 13,526 | 117 | XAUI and clocks | In % of SX95T | 28 | 22 | 47 |
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