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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2012
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Article
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Tab 4
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Research Article
A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection
Table 4
Round-Trip Time for a 1000 B packet: overall and per system component.
Buffer Fill Level
Round-Trip Time
Core
Ring
VEH
Empty
5.5
3.6
1.4
0.5
Half
28.7
9.8
17.4
1.5
Full
51.9
16
33.4
2.5