Research Article
A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication
Table 3
Comparison with software ECDLP implementations.
| Platform | Latency per iteration (ns) | Performance (PA/s) |
| Cell processor at 3.192 GHz, secp112r1 curve [15] | 113 (362 cycles) | 8.81 M | Cell processor, at 3.192 GHz, secp112r1 curve [9] | 142 (453 cycles) | 7.04 M | Cell processor, at 3.192 GHz, ECC2K-130 binary field [10] | 233 (745 cycles) | 4.28 M | Our system, secp112r1 | 1140 (114 cycles) | 878 K: single core 14.05 M: 16 cores |
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