Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application

<table>Ferrers diagram for the partition <svg height="15.0875" id="M143" style="vertical-align:-2.3205pt" version="1.1" viewbox="0 0 89.175003 15.0875" width="89.175003" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,12.138)"><path d="M300 -147l-18 -23q-106 71 -159 185.5t-53 254.5v1q0 139 53 252.5t159 186.5l18 -24q-74 -62 -115.5 -173.5t-41.5 -242.5q0 -130 41.5 -242.5t115.5 -174.5z" id="x28"></path></g><g transform="matrix(.017,-0,0,-.017,5.944,12.138)"><path d="M249 635q70 0 116 -43t46 -105q0 -46 -28 -80q-22 -25 -80 -64q62 -35 97 -75t35 -99q0 -81 -63 -131t-135 -50q-83 0 -137.5 45.5t-54.5 123.5q0 52 45 95q29 28 89 64q-109 62 -109 155q0 66 50.5 115t128.5 49zM238 603q-42 0 -67.5 -31t-25.5 -72q0 -50 32.5 -79.5
t98.5 -62.5q61 48 61 124q0 59 -29.5 90t-69.5 31zM248 20q46 0 76.5 33.5t30.5 89.5q0 50 -39 85.5t-110 71.5q-81 -54 -81 -137q0 -67 35.5 -105t87.5 -38z" id="x38"></path></g><g transform="matrix(.017,-0,0,-.017,19.764,12.138)"><path d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" id="x34"></path></g><g transform="matrix(.017,-0,0,-.017,33.584,12.138)"><path d="M384 0h-275v27q67 5 81.5 18.5t14.5 68.5v385q0 38 -7.5 47.5t-40.5 10.5l-48 2v24q85 15 178 52v-521q0 -55 14.5 -68.5t82.5 -18.5v-27z" id="x31"></path></g><g transform="matrix(.017,-0,0,-.017,47.404,12.138)"><use xlink:href="#x31"></use></g><g transform="matrix(.017,-0,0,-.017,61.241,12.138)"><use xlink:href="#x31"></use></g><g transform="matrix(.017,-0,0,-.017,75.061,12.138)"><use xlink:href="#x31"></use></g><g transform="matrix(.017,-0,0,-.017,83.22,12.138)"><path d="M275 270q0 -296 -211 -440l-19 23q75 62 116.5 174t41.5 243t-42 243t-116 173l19 24q211 -144 211 -440z" id="x29"></path></g>
</svg>.</table>

International Journal of Reconfigurable Computing

fig3

Figure 3

Figure 3: Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application 