An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

Table 1

AIREN resource utilization on V4FX60 FPGA.

No. of ports	Software routing		Hardware routing
	No. of Slice FFs (%)	No. of 4-LUTs (%)	No. of Slice FFs (%)	No. of 4-LUTs (%)
4	433 (0.85%)	669 (1.32%)	305 (0.60%)	655 (1.30%)
8	703 (1.39%)	1,559 (3.08%)	511 (1.01%)	2,009 (3.97%)
16	1,263 (2.49%)	5,589 (11.05%)	964 (1.91%)	8,228 (16.27%)
32	2,471 (4.89%)	20,757 (41.05%)	1,933 (3.82%)	33,603 (66.46%)