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International Journal of Reconfigurable Computing
Volume 2012 (2012), Article ID 736347, 14 pages
http://dx.doi.org/10.1155/2012/736347
Research Article

Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems

CAIAC, Universitat Autònoma de Barcelona, Edifici Enginyeria, Campus UAB, 08193 Bellaterra, Spain

Received 9 March 2012; Revised 17 May 2012; Accepted 19 May 2012

Academic Editor: Patrick R. Schaumont

Copyright © 2012 David Castells-Rufas et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. P. H. W. Leong, “Recent trends in FPGA architectures and applications,” in Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA '08), pp. 137–141, January 2008. View at Publisher · View at Google Scholar · View at Scopus
  2. Altera, Qsys System Integration Tool, http://www.altera.com/products/software/quartus-ii/subscription-edition/qsys/qts-qsys.html.
  3. P. E. McKenney and D. Sarma, “Hard real-time response,” Patent US, 7748003, 2010, http://www.google.com/patents/US7748003.
  4. J. Curreri, S. Koehler, A. George, B. Holland, and R. Garcia, “Performance analysis framework for high-level language applications in reconfigurable computing,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 3, article 5, 2010.
  5. S. Koehler, G. Stitt, and A. D. George, “Platform-aware bottleneck detection for reconfigurable computing applications,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4, no. 3, article 30, 2011. View at Publisher · View at Google Scholar
  6. T. S. J. Sun and R. D. Leu, “Software performance analysis using hardware analyzer,” Patent US, 5903759, 1999, http://ip.com/patfam/xx/25351944.
  7. Altera Corporation, “Design Debugging Using the SignalTap II Embedded Logic Analyzer,” 2007, http://www.altera.com/literature/hb/qts/qts_qii53009.pdf.
  8. Altera Corporation, “Profiling Nios II Systems,” 2005, http://www.altera.com/literature/an/an391.pdf.
  9. J. G. Tong and M. A. S. Khalid, “A comparison of profiling tools for FPGA-based embedded systems,” in Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECD '07), pp. 1687–1690, April 2007. View at Publisher · View at Google Scholar · View at Scopus
  10. L. Shannon and P. Chow, “Using reconfigurability to achieve real-time profiling for hardware/software codesign,” in Proceedings of the 12th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '04), pp. 190–199, February 2004. View at Scopus
  11. D. Castells-Rufas, J. Joven, S. Risueño et al., “MPSoC performance analysis with virtual prototyping platforms,” in Proceedings of the 39th International Conference on Parallel Processing Workshops (ICPPW '10), pp. 154–160, September 2010. View at Publisher · View at Google Scholar · View at Scopus
  12. E. Fernandez-Alonso, D. Castells-Rufas, S. Risueño, J. Carrabina, and J. Joven, “A NoC-based multi-{soft}core with 16 cores,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS '10), pp. 259–262, December 2010. View at Publisher · View at Google Scholar · View at Scopus
  13. A. Knüpfer, H. Brunst, J. Doleschal et al., The Vampir Performance Analysis Tool-Set Tools for High Performance Computing, Springer, 2008.
  14. H. Hübert, B. Stabernack, and K.I. Wels, “Performance and memory profiling for embedded system design,” in Proceedings of the IEEE 2nd International Symposium on Industrial Embedded Systems (SIES '07), pp. 94–101, July 2007. View at Publisher · View at Google Scholar · View at Scopus
  15. M. Montón, A. Portero, M. Moreno, B. Martínez, and J. Carrabina, “Mixed SW/systemC SoC emulation framework,” in Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE '07), pp. 2338–2341, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  16. H. Posadas, F. Herrera, P. Sánchez, E. Villar, and F. Blasco, “System-level performance analysis in systemc,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 1, pp. 378–383, February 2004. View at Publisher · View at Google Scholar · View at Scopus
  17. H. Posadas, S. Real, and E. Villar, M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration Multi-Objective Design Space Exploration of Multiprocessor SOC Architectures: The Multicube Approach, vol. 19, Springer, 2011.
  18. I. Böhm, B. Franke, and N. Topham, “Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator,” in Proceedings of the 10th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS '10), pp. 1–10, July 2010. View at Publisher · View at Google Scholar · View at Scopus
  19. A. Knüpfer, R. Brendel, H. Brunst, H. Mix, and W. E. Nagel, “Introducing the open trace format (OTF),” in Proceedings of the 6th International Conference, Part II, Computational Science (ICCS '06), N. Vassil Alexandrov, G. D. van Albada, M. A. Peter Sloot, and J. Dongarra, Eds., vol. 3992, pp. 526–533, Springer, Reading, UK, May 2006.
  20. J. Balart, A. Duran, M. Gonzàlez, X. Martorell, E. Ayguadé, and J. Labarta, “Nanos mercurium: a research compiler for openmp,” in Proceedings of the European Workshop on OpenMP, vol. 8, 2004.