Research Article
An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H
Table 2
Some design specifications for the ADC.
| Parameter | Value |
| Power supply | 3.3 V | Maximum input bandwidth | 500 kHz | Sampling rate | 11 MHz | Resolution | 6 bits | Full-scale input voltage | 2 | INL | DNL | <0.5 LSB | <1 LSB |
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