An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

Table 3

Specifications for pipeline ADC stages.

Spec	Input	Stage 1	Stage 2
	S&H	4 bits	3 bits
Sub-ADC error 𝑒ADC (bits); Offset voltage 𝑣offset (mV)	16	6; 31.25	3; 125
Gain error 𝑒𝐺 (%)	1.6	12.5
DAC error 𝑒DAC (bits)		6
Noise level (dBc)	−34	−34	−25
Clock jitter	226 ps