Research Article
An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H
Table 4
Prelayout specifications for the ADC.
| | Parameter | Value |
| | Current consumption (rms) | 3.64 mA | | Latency | 5 clock cycles |
| | SNR in the channel | up to | 59.4 | 46.5 dB |
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