An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization

Table 6

Performance achieved/FPGA resource utilization for “one-way” FGO designs.

	Implementation
	Baseline	Stream depth 64	A	B	C	D	E
Resources
Block RAM	641	642	643	642	642	643	1668
Slice Reg	4,816	5,041	9,075	9,265	2,925	7064	3120
Slice LUTS	888,597	888,545	889,151	888,276	888,659	1,768,916	3,133
Slice LUT-FF	890,467	892,889	894,014	896,557	890,878	1,771,482	5,298
Performance
Maximum Freq (MHz)	103.896	108.982	121.772	110.331	106.490	103.331	197.449
Num of Clocks ACL (10 k)	33,680,692	32,710,703	11,843,100	32,613,702	16,203,627	27,352,703	32,710,701
Time	324.18 ms	300.15 ms	97.26 ms	295.60 ms	152.16 ms	264.71 ms	165.67 ms
Speedup over previous	—	1.1x	3.3x	1.1x	2.1x	1.2x	2.0x