Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

Table 1

Hardware modules present in the NIOS II SoPC system.

Component	Clock (MHz)	Interface
NIOS II/f	290	Memory mapped
DDRII SDRAM controller	200	Memory mapped
On-chip RAM	290	Memory mapped
Tightly-coupled RAM	290	Memory mapped
DMA dispatcher (IN)	100	Memory mapped, streaming
DMA write master	100	Memory mapped, streaming
DMA dispatcher (OUT)	200	Memory mapped, streaming
DMA read master	200	Memory mapped, streaming
Feedback/control PIOs	100	Memory mapped
Performance counters	290	Memory mapped