Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="681894.fig.0017a" src="https://static.hindawi.com/articles/ijrc/volume-2013/681894/figures/681894.fig.0017a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Block of the module</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="681894.fig.0017b" src="https://static.hindawi.com/articles/ijrc/volume-2013/681894/figures/681894.fig.0017b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Internal architecture</td></tr></table></td></tr></table>

<table>Simultaneous direct memory read for four rule addresses.</table>

International Journal of Reconfigurable Computing

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Figure 17

Figure 17: Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm 