Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Algorithm 1

Pseudoalgorithm of adjacent partitioning.

Let:  hypergraph = netlist;

  arch_levels = MFPGA levels number;

  Arity[lev] = Arity in MFPGA at level lev;

Phase  1: grouping pairs of dual gates;

Let: sub_hypergraph = hypergraph (level = 1);

phase 2:

for (int lev = arch_levels-1; lev >= 0; lev− −){

 if (lev = 0) {

 partitioning (sub_hypergraph, TopLevelCluster, Arity[lev]);

 // partition instances inside TopLevelCluster into k parts

 // K = Arity[lev]

  } else {

  for (each Cluster in level 1 of the sub_hypergraph) {

  partitioning (sub_hypergraph, Cluster, Arity[lev]);

  // partition instances inside Cluster into k parts

  // K = Arity[lev]

 }

  }

}

phase 3:

uncoarsening sub_hypergraph;