Research Article
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance
Table 10
Mapping of greater circle distance formula.
| | Design | XC4VLX15-12SF363 | | | I/P data | LUT | FF | DSP | SRL | BRAM | CLK (ns)11 | Latency/throughput | IP core |
| | GC (v-HLS) | 16 bit | 22522 | 11937 | 68 | 0 | 20 | 5.31 (Est) | 109/109 | No | | GC (proposed)-D1 | 16 bit | 3113 | 3136 | 4 | 15/3113 | 0 | 5.47 | 24/1 | CORDIC10 | | GC (proposed)-D2 | 16 bit | 1925 | 2062 | 4 | 15/1925 | 0 | 5.38 | 18/1 | CORDIC12 | | GC (proposed)-D3 | 16 bit | 8567 | 8719 | 4 | 33/8567 | 0 | 5.456 | 50/1 | CORDIC13 | | GC (3-terms) | 16 bit | 894 | 3433 | 16 | 0 | 0 | 8.61 | 41/1 | No | | | | 3456 | 3664 | 0 | 0 | 0 | 9.95 | 41/1 | No | | GC (4-terms) | 16 bit | 2145 | 6729 | 21 | 84/2145 | 0 | 8.67 | 59/1 | No | | | | 5375 | 6959 | 0 | 84/5375 | 0 | 9.99 | 59/1 | No |
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Parallel configuration, iteration, and precision: automatic, coarse rotation.
Clock period constraint of 5.5 ns with 0 ns clock jitter.
Parallel architecture, iterations-8, and precision: automatic, coarse rotation.
Parallel architecture, iterations-40, and precision: automatic, coarse rotation.
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