Research Article
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance
Table 6
A function
and corresponding IP cores.
| | Function | IP cores |
| |
→ RND() → InputBW1 → OutputBW1 → None → Serial Arch → Area1 → IPCore1 | | → RND() → InputBW2 → OutputBW2 → Serial I/F → Area2 → IPCore2 | | → RND() → InputBW2 → OutputBW2 → Serial I/F → Area2 → IPCore2 | | → RND() → InputBW3 → OutputBW3 → Parallel I/F → Area3 → IPCore2 | | → RND() → InputBW3 → OutputBW3 → Parallel I/F → Area3 → IPCore2 | | → RND() → InputBW4 → OutputBW4 → None → Area4 → IPCore3 | | → RND() → InputBW5 → OutputBW5 → None → Parallel Arch → Area5 → IPCore4 |
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