IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance

Table 7

Mapping of some representative in-built C functions.

Design	XC4VFX12FF668-10
	I/P Data	LUT	FF	DSP	SRL	BRAM	CLK (ns)	Latency/throughput	IP core
sqrt (v-HLS)	32 bit integer	3105	4308	0	135	0	5.419^1	75^2/75	No
sqrt (proposed)	32 bit integer	358	363	0	0	0	5.323^1	17^3/1	CORDIC
div (v-HLS)	32 bit integer	4342	4105	0	136	0	7.572^4	34^2/34	No
div (proposed); -D1	32 bit integer	1230	1095	13	262/; 1230	0	5.674^4	36/5	Divider^5
div (proposed); -D2	32 bit integer	1224	1011	13	262/; 1230	0	6.769^4	34/5	Divider^5
div (proposed); -D3	32 bit integer	1150	937	13	234/; 1150	0	6.336^4	30/5	Divider^5
div (proposed); -D4	32 bit integer	2279	6720	0	72/; 2279	0	6.820^4	68/1	Divider^5
div (proposed); -D5	32 bit integer	1284	3244	0	68/; 1284	0	5.607^4	36/1	Divider^6
div (proposed); -D6	32 bit integer	1253	1971	0	4/; 1253	0	7.885	37/2	Divider^6
abs (v-HLS)	16 bit integer	51	19	0	0	0	2.462	1/1	No
abs (proposed)	16 bit integer	32	32	0	0	0	3.121	1/1	Yes

1Clock period constraint of 4.5 ns with input jitter of 0.56 ns (clock uncertainty).
2Worst case and best case latencies.
3Maximum latency.
4Clock period constraint of 8 ns with input jitter of 1 ns (clock uncertainty).
5CORDIC configuration of integer quotient and fractional remainder with maximum pipelining.
6CORDIC configuration of integer quotient and integer remainder with maximum pipelining.