FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

Table 2

The performance advantage of our QPSK ADCRL in locked-in frequency range.

SNR	Architecture	Maximal locked-in	Locked-in time (ms)	Steady-phase error (degree)
		Frequency Range (KHZ)
20 db	QPSK ADCOL	±170	0.18	Approximating to 0
20 db	Our QPSK ADCRL	±680	0.05	Approximating to 0
5 db	QPSK ADCOL	±120	0.4	Approximating to 2
5 db	Our QPSK ADCRL	±510	0.13	Approximating to 4