FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

Table 3

The hardware cost of the different modules for our QPSK ADCRL.

Module		Number of slice registers	Number of slice LUTs	Number used as logic
QPSK ADCOL		174 out of 28800	580 out of 28800	612 out of 28800
MLFOE	FD	875 out of 28800	892 out of 28800	790 out of 28800
	MLFE	603 out of 28800	516 out of 28800	592 out of 28800
Total hardware cost		1652 out of 28800	1988 out of 28800	1994 out of 28800