Research Article
FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator
Table 4
The power consumption of our QPSK ADCRL for different operating frequencies.
| Clock frequency (MHZ) | Dynamic power (W) | Quiescent power (W) | Total power (W) | Junction temp. (C) |
| 312 | 0.060 | 0.526 | 0.594 | 50.9 | 250 | 0.058 | 0.526 | 0.583 | 51 | 200 | 0.048 | 0.525 | 0.574 | 51 | 150 | 0.039 | 0.525 | 0.564 | 50.9 |
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